AR# 63739 Kintex UltraScale FPGA KCU105 Evaluation Kit - Board Debug Checklist

忘是亡心i 2022-05-16 12:37 136阅读 0赞

## Description ##

The Kintex UltraScale FPGA KCU105 Evaluation Kit Checklist is useful to debug board-related issues and to determine if applying for a Board RMA is the next step.

Before working through the KCU105 Board Debug Checklist, please review [(Xilinx Answer 63175)][Xilinx Answer 63175] \- *Kintex UltraScale KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record*, as the issue you are faced with might be covered there.

## Solution ##

![63739-1_201503021233353416.jpg][]

**Figure 63739-1: KCU105**

**Table 63739-1: Callouts**

![63739-2_201503021244396057.jpg][]

**1. [Switch / Jumper Settings][Switch _ Jumper Settings]**  
**2.[Board Power][]  
3.[Cable detection][]  
4.[JTAG Initialization][]**

**The following debug steps assume steps 1-4 have been checked and are working:**  
**5.[JTAG Configuration][]  
6.[Master SPI Configuration][]  
7.[PCIe][]**  
**8.[IBERT][]  
9.[DDR4][]  
10.[Interface Tests][]  
11.[Known Issues for KCU105][]**

[ ][Known Issues for KCU105]

**1. Switch / Jumper Settings  
  
Default Switch and Jumper Settings for the KCU105 are:**  
  
Start from a known safe scenario by verifying the default Switch and Jumper settings. You can then set switches / jumpers for your application.

a. *DIP Switch Default Settings*:  
![63739-3_201503021319316213.jpg][]  
  
  
b. *DIP Switch SW15 Mode Settings:*  
  
Mode settings switches M2:0\] are wired to SW15 pins 4-6. The default settings for SW15 (Mode Settings) is listed below.

![63739-4_201503021259365209.jpg][]

c. *Default Jumper Settings:*

![63739-5_201507270517083757.jpg][]

**2. Board Power**

Power-ON LEDs: Initial power testing is performed on the bench using the AC-to-DC power adapter provided in the KCU105 Evaluation Kit.

The status of the Power-ON LEDs is an indication of board health.

a. Check the status of the following LEDs at Power-ON:

![63739-12_201503031748007058.jpg][]

![63739-13_201503031851351892.jpg][]  
  
  
b. Ethernet PHY status LEDs  
  
These LEDs are visible on the left edge of the KCU105 board when it is installed into a PCIe slot in a PC chassis.  
  
The two PHY status LEDs are integrated into the metal frame of the P3 RJ-45 connector, as shown below:

![63739-6_201503021738239082.jpg][]  
  
  
c. Voltage and current monitoring and control for the Maxim Integrated power system is available through either the KCU105 system controller or via the Maxim Integrated PowerTool software graphical user interface.

The KCU105 system controller is the simplest and most convenient way to monitor the voltage and current values for the power rails on the board. More information on the System Controller can be found in *(UG917) The KCU105 Board User Guide*.  
[http://www.xilinx.com/support/documentation/boards\_and\_kits/kcu105/ug917-kcu105-eval-bd.pdf][http_www.xilinx.com_support_documentation_boards_and_kits_kcu105_ug917-kcu105-eval-bd.pdf]

The Maxim Integrated InTune power controllers can also be accessed through the PMBus connector J39.  
Using this connector requires the Maxim PowerTool USB cable (Maxim part number MAXPOWERTOOL002\#).

If the Power ON LEDs are not lit at power on, you may need to reprogram the Maxim Integrated Power Controllers on your KCU105.  
This can be done using the Maxim Integrated PowerTool software package, and the Maxim Integrated Dongle.

Information on the Maxim Integrated Power Solution on the KCU105 can be found in [(Xilinx Answer 65236)][Xilinx Answer 65236], together with information on how to order a Maxim Integrated USB cable free of charge.  
  
The Maxim Integrated Power Controllers on the KCU105 can be reprogrammed. This is the first debug that should be taken if power issues are discovered on your KCU105.  
Step-by-step instructions, together with the script to be used to reprogram the Maxim parts can be found in [(Xilinx Answer 65218)][Xilinx Answer 65218].

d. If the 12V Power LED (DS26 on the KCU105) is not Green upon power up, then 12VDC is not being delivered to the KCU105 power input connector.  
  
Follow these steps:

![63739-17.jpg][]

**3. Cable detection**

The KCU105 uses a USB A-to-micro-B cable plugged into the KCU105 Digilent USB-to-JTAG module, U115.

A 2-mm JTAG header (J3) is also provided in parallel for access by Xilinx download cables such as the Platform Cable USB II.  
  
**a. USB A-to-micro-B cable:**

1.  Is the cable visible in Device Manager?  
      
    If the three items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.  
    ![50079-16_201302130736200115.jpg][]
2.  Are cable drivers loaded correctly? Drivers for this cable should be included in the Vivado Design Tools installation.  
    However, if problems are experienced with USB A-to-micro-B cable connection, a Digilent plug-in can be downloaded from the link below.  
    For installation, please follow the guidelines in the document provided in the downloaded files:  
    [http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN][http_digilentinc.com_Products_Detail.cfm_NavPath_2_66_768_Prod_DIGILENT-PLUGIN].  
    This plug-in requires Adept systems 2.4 or later for Windows and Adept systems 2.3.9 or later for Linux.  
    Adept software is available from Digilent:  
    [http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2][http_digilentinc.com_Products_Detail.cfm_NavPath_2_66_828_Prod_ADEPT2].  
    
3.  Check system properties and environment variables.  
    For information on environment variables, see [(Xilinx Answer 11630)][Xilinx Answer 11630].  
    
4.  Is the USB port enabled?  
    You can reboot your system to re-initialize the USB buses.  
    
5.  Are Xilinx tools correctly installed? (Vivado Hardware Manager or ILA)  
    For supported software version information, see the Kit Product Page:  
    [http://www.xilinx.com/products/boards-and-kits/kcu105.html\#overview][http_www.xilinx.com_products_boards-and-kits_kcu105.html_overview]  
    If an issue is suspected with tools installation, see the Installation and Licensing Guide (make sure to use the most recent version of tools and associated documentation which supports the KCU105).  
    [http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2014\_4/ug973-vivado-release-notes-install-license.pdf][http_www.xilinx.com_support_documentation_sw_manuals_xilinx2014_4_ug973-vivado-release-notes-install-license.pdf]  
    
6.  Is the Operating System (OS) being used Windows 7?  
    If so, please see [(Xilinx Answer 41442)][Xilinx Answer 41442] and [(Xilinx Answer 44397)][Xilinx Answer 44397].

**b. Platform Cable USB II**

1.  Is the cable visible in Device Manager?  
    ![54139-17_201305080614473542.jpg][]
2.  Are cable drivers loaded correctly? Drivers for this cable should be included in the Vivado Design Tools installation.  
    However, if problems are experienced with the Platform Cable USB II connection, please follow the uninstall and reinstall instructions in [(Xilinx Answer 44397)][Xilinx Answer 44397].  
    
3.  Check system properties and environment variables.  
    For information on environment variables, see [(Xilinx Answer 11630)][Xilinx Answer 11630].  
    
4.  Is the USB port enabled? You can reboot your system to re-initialize the USB buses.  
    
5.  Are Xilinx tools correctly installed? (Hardware Manager or ILA)  
    For supported software version information, see the Kit Product Page:  
    [http://www.xilinx.com/products/boards-and-kits/kcu105.html\#overview][http_www.xilinx.com_products_boards-and-kits_kcu105.html_overview]  
    If an issue is suspected with tools installation, see the Installation and Licensing Guide (make sure to use the most recent version of tools and associated documentation which supports the KCU105).  
    [http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2014\_4/ug973-vivado-release-notes-install-license.pdf][http_www.xilinx.com_support_documentation_sw_manuals_xilinx2014_4_ug973-vivado-release-notes-install-license.pdf]  
    
6.  Is the Operating System (OS) being used Windows 7?  
    If so, please see [(Xilinx Answer 41442)][Xilinx Answer 41442] and [(Xilinx Answer 44397)][Xilinx Answer 44397].

If the above steps do not enable you to connect, please review the [Support Webpage][] for your available Support options.

**4. JTAG Initialization**  
  
The status of the board JTAG chain is checked using Xilinx Tools (Hardware Manager in Vivado).

To check to see that the JTAG chain is initialized correctly, follow this JTAG Initialization Test Case:  
  
1. Remove any FMC cards from KCU105.  
2. Set the mode switch SW15 for JTAG mode (101).

![63739-8_201503021820188646.jpg][]  
  
3. Power up KCU105 on the bench (not in a PC chassis).  
4. Connect the Digilent USB A-to-micro B cable to the KCU105 (through the Digilent onboard USB-to-JTAG configuration logic module - U115 - through header J87).  
5. Check that the Digilent device shows up in the Device Manager.  
6. Ensure Xilinx tools (Vivado 2014.4.1 or later - preferably the latest version of tools that support the KCU105) are correctly installed.  
7. Launch Vivado Hardware Manager - is the cable identified correctly?

*  If not, see section [3. Cable detection][Cable detection] above.
 *  If yes, but Vivado Hardware Manager did not discover and display the JTAG chain, slow down the cable speed (**Output** > **Cable Setup**).
 *  If yes, but Vivado Hardware Manager did not discover and display the JTAG chain and slowing the cable speed does not resolve the issue, see the following (assumes Digilent USB A-to-micro B cable is plugged into USB-to-JTAG configuration logic module U115 through J87):  
    ![63739-18_201509152015305095.jpg][]

If following the above steps does not allow you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC.

Connect the Platform Cable USB to header J3, and connect to your PC.  
  
Ensure Xilinx tools (preferably the latest version of tools that support the KCU105) are correctly installed.

Launch Vivado Hardware Manager - is the cable identified correctly?  
  
If following the above steps does not allow you to initialize the JTAG chain, please review the Support Webpage for your available Support options.

[http://www.xilinx.com/support/clearexpress/websupport.htm][http_www.xilinx.com_support_clearexpress_websupport.htm]  
  
  
**5. JTAG Configuration**  
  
If the JTAG chain initializes okay but JTAG configuration fails, check the following:  
  
a) Verify the mode switch settings for JTAG configuration mode:  
SW15-2 (M2) 1  
SW15-3 (M1) 0  
SW15-4 (M0) 1

b) In Vivado Hardware Manager, select a lower cable frequency and re-attempt configuration.

![device_20ident_201503251117292879.JPG][]

c) Pulse the PROG push button on the KCU105 (SW4).

Pulsing PROG will clear out any problems caused by power up ramp rate issues to the FPGA.

d) Review [(Xilinx Answer 34904)][Xilinx Answer 34904] \- Xilinx Configuration Solution Center.

The Configuration Solution Center is available to address all questions related to Configuration.  
  
If the above steps fail to enable JTAG configuration, please review the [Support Webpage][http_www.xilinx.com_support_clearexpress_websupport.htm] for your available Support options.

**6.Master SPI configuration**  
  
The Vivado Hardware Manager can be used to indirectly program the dual-QSPI flash devices (U35, U36) on the KCU105.

With both SW15.6 (FPGA\_M2) and SW15.5 (SYSCTLR\_ENABLE) in the OFF (disable the SYSCTLR\_ENABLE) position, a bitstream programmed into the dual-QSPI flash devices (U35, U36) is used to configure the UltraScale FPGA U1.

If you have loaded a ".mcs" file into the SPI flash on the KCU105, and subsequent Master SPI configuration of the Kintex UltraScale device fails, the following points should be checked:

a. If the ".mcs" file is correctly loaded, you will see the selected FLASH device added to the JTAG chain, as shown here:

![flash_20programmed_201503251119100906.JPG][]By clicking on the flash device, you will see the MCS file succesfully loaded:

![flash_20programmed2_201503251120380957.JPG][]

If you do not see the FLASH device attached to the XCKU040 device as shown, see the Vivado Design Suite User Guide: (UG908) *Programming and Debugging*.

[http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2014\_4/ug908-vivado-programming-debugging.pdf][http_www.xilinx.com_support_documentation_sw_manuals_xilinx2014_4_ug908-vivado-programming-debugging.pdf]

b. Verify the mode switch settings for Master SPI configuration:  
S15-6 (M2) 0  
S15-5 (M1) 0  
S15-4 (M0) 1  
  
c. In Vivado Hardware Manager, select a lower cable frequency and re-attempt configuration.

d. Pulse the PROG push button on the KCU105 (SW4), to attempt to reload the FPGA with the configuration image.

e. Review [(Xilinx Answer 34904)][Xilinx Answer 34904] *- Xilinx Configuration Solution Center.*

The Configuration Solution Center is available to address all questions related to Configuration.  
  
If the above steps fail to enable SPI configuration, please review the [Support Webpage][] for your available Support options.

**7. PCIe**  
  
If the KCU105 configures correctly, but the PCIe interface does not operate as expected, check the following:  
  
a) Do NOT plug a PC ATX power supply 6-pin connector into J15 on the KCU105 board.

The ATX 6-pin connector has a different pinout than J15.

Connecting an ATX 6-pin connector into J15 will damage the KCU105 board and void the board warranty.

To install and power the board correctly, follow the instructions given in (UG917) KCU105 Evaluation Board User Guide - Appendix E - Board Setup.

[http://www.xilinx.com/support/documentation/boards\_and\_kits/kcu105/ug917-kcu105-eval-bd.pdf][http_www.xilinx.com_support_documentation_boards_and_kits_kcu105_ug917-kcu105-eval-bd.pdf]  
  
b) Check J74, lane width, is set correctly for your application.  
  
c) See one of the following Answer Records, covering Known Issues for PCI Express, including Kintex UltraScale:

[(Xilinx Answer 57945)][Xilinx Answer 57945] \- UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.3 and newer tools versions.  
  
d) Download and run the KCU105 PCIe Example Design, whichever version is appropriate for your silicon and software version.

It is recommended to always use the latest version of software which supports the KCU105, and associated version of the KCU105 PCIe Example Design.

Follow the associated PDF.

All are available from the KCU105 Example Designs page.

[http://www.xilinx.com/products/boards-and-kits/kcu105.html][http_www.xilinx.com_products_boards-and-kits_kcu105.html]

![63739-14_201503041813264988.jpg][]

e) Read the KCU105 PCIe Example Design document: KCU105 PDF: xtp350.pdf and follow the instructions within.  
  
h) Review [(Xilinx Answer 34536)][Xilinx Answer 34536] \- Xilinx Solution Center for PCI Express.

The Solution Center for PCI Express is available to address all questions related to the Xilinx solutions for PCI Express.

If the above steps fail to resolve the PCIe issue, please review the [Support Webpage][] for your available Support options.

**8. IBERT**  
  
**NOTE:** Running IBERT requires the installation of Vivado ILA.

A device-locked license for this software is provided with the Kintex UltraScale KCU105 Evaluation Kit.

If the KCU105 configures correctly, but IBERT does not operate as expected, check the following:  
  
a) If using MGT loopback, ensure that you have the correct equipment, including SMA cables, SMA Quick connects and Connect Optical Loopback Adapter:

![50079-21_201302150324270364.jpg][]![50079-20_201302150324469434.jpg][]![50079-22_201302150325058816.jpg][]

More information can be found in the KCU105 GTH IBERT PDF, from the KCU105 Example Designs page.

[http://www.xilinx.com/products/boards-and-kits/kcu105.html][http_www.xilinx.com_products_boards-and-kits_kcu105.html]  
  
b) Download and run the KCU105 GTH IBERT Example Design, whichever version is appropriate for your silicon and software version.

It is recommended to always use the latest version of software which supports the KCU105, and associated version of the KCU105 GTH IBERT Example Design.  
  
Follow the associated PDF.

All are available from the KCU105 Example Designs page.

[http://www.xilinx.com/products/boards-and-kits/kcu105.html][http_www.xilinx.com_products_boards-and-kits_kcu105.html]

![63739-15_201503041818282916.jpg][].  
c) Read the KCU105 GTH IBERT Example Design document: KCU105 GTH IBERT PDF: xtp346.pdf and follow the instructions therein.

d) IBERT Design Assistant: [(Xilinx Answer 45562)][Xilinx Answer 45562].  
  
If the above steps fail to resolve the IBERT issue, please review the [Support Webpage][] for your available Support options.

**9.DDR4**  
  
If a problem is suspected with DDR4 / MIG, check the following:  
  
a) Ensure that the DDR4 DIMM component memory is inserted correctly.

b) Download and run the KCU105 MIG Example Design, whichever version is appropriate for your silicon and software version.

It is recommended to always use the latest version of software which supports the KCU105, and associated version of the KCU105 MIG Example Design.

Follow the associated PDF.

All are available from the KCU105 Example Designs page.

[http://www.xilinx.com/products/boards-and-kits/kcu105.html][http_www.xilinx.com_products_boards-and-kits_kcu105.html]

![63739-16_201503041827127337.jpg][]![63739-16_201503041827127337.jpg 1][]  
c) Read the KCU105 MIG Example Design document: KCU105 MIG PDF: xtp348.pdf

d) Review [(Xilinx Answer 34243)][Xilinx Answer 34243] \- Xilinx MIG Solution Center.

The Memory Interface Generator (MIG) Solution Center is available to address all questions related to MIG.  
  
If the above steps fail to resolve the DDR4 issue, please review the [Support Webpage][] for your available Support options.

**10. Interface Tests**  
  
[(Xilinx Answer 63799)][Xilinx Answer 63799] \- Kintex UltraScale FPGA KCU105 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the KCU105 are working correctly.

This Answer Record forms part of [(Xilinx Answer 43748)][Xilinx Answer 43748] \- Xilinx Boards and Kits Debug Assistant.

If the above tests fail to resolve the issue, please review the [Support Webpage][] for your available Support options.

**11. Known Issues for KCU105**  
  
All Known Issues for the Kintex UltraScale FPGA KCU105 Evaluation Kit are listed in [(Xilinx Answer 63175)][Xilinx Answer 63175] \- Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record.

If the issue you are faced with is not listed in the Known Issues and Release Notes Master Answer Record, and the steps above fail to resolve the issue, please review the [Support Webpage][] for your available Support options.

[Xilinx Answer 63175]: https://www.xilinx.com/support/answers/63175.html
[63739-1_201503021233353416.jpg]: /images/20220516/b4b7ac016438457192e4f6e0aa31696e.png
[63739-2_201503021244396057.jpg]: /images/20220516/4531e7fab59e4e0386c23e026ad3a0f8.png
[Switch _ Jumper Settings]: https://www.xilinx.com/support/answers/63739.html#switch
[Board Power]: https://www.xilinx.com/support/answers/63739.html#board
[Cable detection]: https://www.xilinx.com/support/answers/63739.html#cable
[JTAG Initialization]: https://www.xilinx.com/support/answers/63739.html#JTAGinit
[JTAG Configuration]: https://www.xilinx.com/support/answers/63739.html#JTAGconfig
[Master SPI Configuration]: https://www.xilinx.com/support/answers/63739.html#masterSPI
[PCIe]: https://www.xilinx.com/support/answers/63739.html#PCIe
[IBERT]: https://www.xilinx.com/support/answers/63739.html#IBERT
[DDR4]: https://www.xilinx.com/support/answers/63739.html#DDR
[Interface Tests]: https://www.xilinx.com/support/answers/63739.html#tests
[Known Issues for KCU105]: https://www.xilinx.com/support/answers/63739.html#known
[63739-3_201503021319316213.jpg]: /images/20220516/acef81bb9c60409e99cb56d4de3e82e8.png
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[63739-5_201507270517083757.jpg]: /images/20220516/9eee6c8440bc4e0b9b1311c5331b045a.png
[63739-12_201503031748007058.jpg]: /images/20220516/44466f87c30641fd8b749d20fbdee24c.png
[63739-13_201503031851351892.jpg]: /images/20220516/74578405081640f889041c4497456ed7.png
[63739-6_201503021738239082.jpg]: /images/20220516/44a19c77728e43cbae9ac343810141ec.png
[http_www.xilinx.com_support_documentation_boards_and_kits_kcu105_ug917-kcu105-eval-bd.pdf]: http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf
[Xilinx Answer 65236]: https://www.xilinx.com/support/answers/65236.html
[Xilinx Answer 65218]: https://www.xilinx.com/support/answers/65218.html
[63739-17.jpg]: /images/20220516/d9df9909c2ef46938c398e5d3a09c61a.png
[50079-16_201302130736200115.jpg]: /images/20220516/7b8de975dfc4453b9b2ede451b688c2d.png
[http_digilentinc.com_Products_Detail.cfm_NavPath_2_66_768_Prod_DIGILENT-PLUGIN]: http://digilentinc.com/Products/Detail.cfm?NavPath=2%2C66%2C768&Prod=DIGILENT-PLUGIN
[http_digilentinc.com_Products_Detail.cfm_NavPath_2_66_828_Prod_ADEPT2]: http://digilentinc.com/Products/Detail.cfm?NavPath=2%2C66%2C828&Prod=ADEPT2
[Xilinx Answer 11630]: https://www.xilinx.com/support/answers/11630.html
[http_www.xilinx.com_products_boards-and-kits_kcu105.html_overview]: http://www.xilinx.com/products/boards-and-kits/kcu105.html#overview
[http_www.xilinx.com_support_documentation_sw_manuals_xilinx2014_4_ug973-vivado-release-notes-install-license.pdf]: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug973-vivado-release-notes-install-license.pdf
[Xilinx Answer 41442]: https://www.xilinx.com/support/answers/41442.html
[Xilinx Answer 44397]: https://www.xilinx.com/support/answers/44397.html
[54139-17_201305080614473542.jpg]: /images/20220516/c8e7846f80084f9983bd473d69b7945c.png
[Support Webpage]: http://www.xilinx.com/support/service-portal.html
[63739-8_201503021820188646.jpg]: /images/20220516/fa82e219161b4f9ba3aa4a59b173e3ad.png
[63739-18_201509152015305095.jpg]: /images/20220516/21d7d1f084a146938447841ad5a8eb97.png
[http_www.xilinx.com_support_clearexpress_websupport.htm]: http://www.xilinx.com/support/clearexpress/websupport.htm
[device_20ident_201503251117292879.JPG]: https://www.xilinx.com/Image/device%20ident_201503251117292879.JPG
[Xilinx Answer 34904]: https://www.xilinx.com/support/answers/34904.html
[flash_20programmed_201503251119100906.JPG]: https://www.xilinx.com/Image/flash%20programmed_201503251119100906.JPG
[flash_20programmed2_201503251120380957.JPG]: https://www.xilinx.com/Image/flash%20programmed2_201503251120380957.JPG
[http_www.xilinx.com_support_documentation_sw_manuals_xilinx2014_4_ug908-vivado-programming-debugging.pdf]: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug908-vivado-programming-debugging.pdf
[Xilinx Answer 57945]: https://www.xilinx.com/support/answers/57945.html
[http_www.xilinx.com_products_boards-and-kits_kcu105.html]: http://www.xilinx.com/products/boards-and-kits/kcu105.html
[63739-14_201503041813264988.jpg]: https://www.xilinx.com/Image/63739-14_201503041813264988.jpg
[Xilinx Answer 34536]: https://www.xilinx.com/support/answers/34536.html
[50079-21_201302150324270364.jpg]: https://www.xilinx.com/content/dam/xilinx/Image/50079-21_201302150324270364.jpg
[50079-20_201302150324469434.jpg]: https://www.xilinx.com/content/dam/xilinx/Image/50079-20_201302150324469434.jpg
[50079-22_201302150325058816.jpg]: /images/20220516/e4506bfd542c49e5b8f67c7fc126154e.png
[63739-15_201503041818282916.jpg]: https://www.xilinx.com/Image/63739-15_201503041818282916.jpg
[Xilinx Answer 45562]: https://www.xilinx.com/support/answers/45562.html
[63739-16_201503041827127337.jpg]: https://www.xilinx.com/Image/63739-16_201503041827127337.jpg
[63739-16_201503041827127337.jpg 1]: https://www.xilinx.com/content/dam/xilinx/Image/63739-16_201503041827127337.jpg
[Xilinx Answer 34243]: https://www.xilinx.com/support/answers/34243.html
[Xilinx Answer 63799]: https://www.xilinx.com/support/answers/63799.html
[Xilinx Answer 43748]: https://www.xilinx.com/support/answers/43748.html