HI3518E平台ISP调试环境搭建

迷南。 2022-05-22 04:45 236阅读 0赞

[https://blog.csdn.net/dddxxxx/article/details/77451196][https_blog.csdn.net_dddxxxx_article_details_77451196]

海思的SDK提供了ISP调试的相关工具，降低了IPC开发ISP调试的难度。初次搭建ISP调试环境，记录一下。

SDK版本：Hi3518\_MPP\_V1.0.A.0

硬件平台：HI3518E\_OV9732

工具包：PQ\_TOOL (Hi3518E\_V100R001C01SPC0A0\\01.software\\pc\\PQ\_TOOL)

文件说明：Hi3518\_ITTB\_MPP2\_V1.0.A.0\_B030.tgz 设备端工具 ； PQTools\_V3.7.5.zip PC端工具

环境搭建步骤：

（1）将Hi3518\_ITTB\_MPP2\_V1.0.A.0\_B030.tgz拷贝至nfs共享目录名，解压后运行HiIspTool.sh脚本

倘若用海思自带的工具出图像并调节ISP运行：

\#./HiIspTool.sh -a -p ov9732\_720p\_line.ini

ps一下可以看到两个进程

696 adminlvj 58488 S ./ittb\_stream -p ov9732\_720p\_line.ini  
699 adminlvj 19676 S ./ittb\_control

倘若运行自己的工程出图像了，这时只需要运行一下命令即可。

\#./HiIspTool.sh -a

ps一下可以看到一个进程

699 adminlvj 19676 S ./ittb\_control

（2）PC端直接解压PQTools\_V3.7.5.zip，运行HiPQTools.exe，输入选择sdk版本Hi3518\_MPP\_V1.0.A.0 ，输入设备IP，就可以连接上摄像头

![50040963][]

倘若运行了ittb\_stream，可以PC端软件上打开视频图像窗口

![50040963][]

连接成功，至此，最简单的ISP调试环境搭建就完成了。复杂的就是后面的ISP调节过程了。

备注：

运行脚本的时候可能会报错，查看相关打印信息，将错误消除。当前产品我们用的是HI3518E+OV9732，SDK中并没有提供相关的sensor库和相关的config文件，所以运行报错了！

解决：将OV9732sensor库拷贝至Hi3518\_ITTB\_MPP2\_V1.0.A.0/libs/下，将ov9732\_720p\_line.ini拷贝至Hi3518\_ITTB\_MPP2\_V1.0.A.0/configs/下

附录：

ov9732\_720p\_line.ini

\[plain\] [view plain][] [copy][view plain]

1.  \[sensor\] 
2.  Sensor\_type =ov9732 ;the type of sensor 
3.  Mode =0 ;LINE mode,mode = 0 ,WDR mode,mode =1 
4.  DllFile =libs/libsns\_ov9732.so ;LineDllFile path 
5.  
6.  \[vi\_dev\] 
7.  Input\_mod =2 ;VI\_INPUT\_MODE\_BT656 = 0 
8.   ;VI\_INPUT\_MODE\_BT601, 
9.   ;VI\_INPUT\_MODE\_DIGITAL\_CAMERA 
10. 
11. Work\_mod =0 ;VI\_WORK\_MODE\_1Multiplex = 0 
12. 
13.  ;VI\_WORK\_MODE\_2Multiplex, 
14. 
15.  ;VI\_WORK\_MODE\_4Multiplex 
16. 
17. Combine\_mode =0 ;Y/C composite or separation mode 
18. 
19.  ;VI\_COMBINE\_COMPOSITE = 0 /\*Composite mode \*/ 
20. 
21.  ;VI\_COMBINE\_SEPARATE, /\*Separate mode \*/ 
22. 
23. Comp\_mode =0 ;Component mode (single-component or dual-component) 
24. 
25.  ;VI\_COMP\_MODE\_SINGLE = 0, /\*single component mode \*/ 
26. 
27.  ;VI\_COMP\_MODE\_DOUBLE = 1, /\*double component mode \*/ 
28. 
29. Clock\_edge =1 ;Clock edge mode (sampling on the rising or falling edge) 
30. 
31.  ;VI\_CLK\_EDGE\_SINGLE\_UP=0, /\*rising edge \*/ 
32. 
33.  ;VI\_CLK\_EDGE\_SINGLE\_DOWN, /\*falling edge \*/ 
34. 
35. Mask\_num =2 ;Component mask 
36. 
37. Mask\_0 =0xFFC00000 
38. 
39. Mask\_1 =0x0 
40. 
41. Scan\_mode = 1;VI\_SCAN\_INTERLACED = 0 
42. 
43.  ;VI\_SCAN\_PROGRESSIVE, 
44. 
45. Data\_seq =2 ;data sequence (ONLY for YUV format) 
46. 
47.  ;----2th component U/V sequence in bt1120 
48. 
49.  ; VI\_INPUT\_DATA\_VUVU = 0, 
50. 
51.  ; VI\_INPUT\_DATA\_UVUV, 
52. 
53.  ;----input sequence for yuv 
54. 
55.  ; VI\_INPUT\_DATA\_UYVY = 0, 
56. 
57.  ; VI\_INPUT\_DATA\_VYUY, 
58. 
59.  ; VI\_INPUT\_DATA\_YUYV, 
60. 
61.  ; VI\_INPUT\_DATA\_YVYU 
62. 
63. 
64. 
65. Vsync =1 ; vertical synchronization signal 
66. 
67.  ;VI\_VSYNC\_FIELD = 0, 
68. 
69.  ;VI\_VSYNC\_PULSE, 
70. 
71. VsyncNeg=0 ;Polarity of the vertical synchronization signal 
72. 
73.  ;VI\_VSYNC\_NEG\_HIGH = 0, 
74. 
75.  ;VI\_VSYNC\_NEG\_LOW /\*if VIU\_VSYNC\_E 
76. 
77. Hsync =0 ;Attribute of the horizontal synchronization signal 
78. 
79.  ;VI\_HSYNC\_VALID\_SINGNAL = 0, 
80. 
81.  ;VI\_HSYNC\_PULSE, 
82. 
83. HsyncNeg =0 ;Polarity of the horizontal synchronization signal 
84. 
85.  ;VI\_HSYNC\_NEG\_HIGH = 0, 
86. 
87.  ;VI\_HSYNC\_NEG\_LOW 
88. 
89. VsyncValid =0 ;Attribute of the valid vertical synchronization signal 
90. 
91.  ;VI\_VSYNC\_NORM\_PULSE = 0, 
92. 
93.  ;VI\_VSYNC\_VALID\_SINGAL, 
94. 
95. VsyncValidNeg =0;Polarity of the valid vertical synchronization signal 
96. 
97.  ;VI\_VSYNC\_VALID\_NEG\_HIGH = 0, 
98. 
99.  ;VI\_VSYNC\_VALID\_NEG\_LOW 
100. 
101. Timingblank\_HsyncHfb =0 ;Horizontal front blanking width 
102. 
103. Timingblank\_HsyncAct =1280 ;Horizontal effetive width 
104. 
105. Timingblank\_HsyncHbb =0 ;Horizontal back blanking width 
106. 
107. Timingblank\_VsyncVfb =0 ;Vertical front blanking height 
108. 
109. Timingblank\_VsyncVact =720 ;Vertical effetive width 
110. 
111. Timingblank\_VsyncVbb=0 ;Vertical back blanking height 
112. 
113. Timingblank\_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive) 
114. 
115. Timingblank\_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) 
116. 
117. Timingblank\_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) 
118. 
119. 
120. 
121. ;----- only for bt656 ---------- 
122. FixCode =0 ;BT656\_FIXCODE\_1 = 0, 
123. 
124.  ;BT656\_FIXCODE\_0 
125. 
126. FieldPolar=0 ;BT656\_FIELD\_POLAR\_STD = 0 
127. 
128.  ;BT656\_FIELD\_POLAR\_NSTD 
129. 
130. DataPath =1 ;ISP enable or bypass 
131. 
132.  ;VI\_PATH\_BYPASS = 0,/\* ISP bypass \*/ 
133. 
134.  ;VI\_PATH\_ISP = 1,/\* ISP enable \*/ 
135. 
136.  ;VI\_PATH\_RAW = 2,/\* Capture raw data, for debug \*/ 
137. 
138. InputDataType=1 ;VI\_DATA\_TYPE\_YUV = 0,VI\_DATA\_TYPE\_RGB = 1, 
139. 
140. DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1 
141. 
142. 
143. \[vi\_chn\] 
144. 
145. CapRect\_X =0 
146. 
147. CapRect\_Y =0 
148. 
149. CapRect\_Width=1280 
150. 
151. CapRect\_Height=720 
152. 
153. DestSize\_Width=1280 
154. 
155. DestSize\_Height=720 
156. 
157. CapSel =2 ;Frame/field select. ONLY used in interlaced mode 
158.  ;VI\_CAPSEL\_TOP = 0, /\* top field \*/ 
159.  ;VI\_CAPSEL\_BOTTOM, /\* bottom field \*/ 
160.  ;VI\_CAPSEL\_BOTH, /\* top and bottom field \*/ 
161. 
162. PixFormat =19 ; 
163. 
164. 
165. 
166. SrcFrameRate=-1 ;Source frame rate. -1: not controll 
167. 
168. FrameRate =-1 ;Target frame rate. -1: not controll 
169. 
170. 
171. \[vpss\_group\] 
172. Vpss\_DrEn =FALSE 
173. 
174. Vpss\_DbEn =FALSE 
175. 
176. Vpss\_IeEn =TRUE 
177. 
178. Vpss\_NrEn =TRUE 
179. 
180. Vpss\_HistEn =TRUE 
181. 
182. Vpss\_DieMode=0 ;Define de-interlace mode 
183. 
184.  ;VPSS\_DIE\_MODE\_AUTO = 0, 
185. 
186.  ;VPSS\_DIE\_MODE\_NODIE = 1, 
187. 
188.  ;VPSS\_DIE\_MODE\_DIE = 2, 
189. 
190. \[vpss\_chn\] 
191. Vpss\_W =1280 
192. Vpss\_H =720 
193. 
194. \[isp\_image\] 
195. 
196. Isp\_W =1280 
197. 
198. Isp\_H =720 
199. 
200. Isp\_FrameRate=30 
201. 
202. Isp\_Bayer =3 ;BAYER\_RGGB=0, BAYER\_GRBG=1, BAYER\_GBRG=2, BAYER\_BGGR=3 
203. 
204. 
205. \[isp\_timing\] 
206. 
207. Isp\_WndMode=0 ;WIND\_NONE= 0,WIND\_HOR= 1,WIND\_VER= 2,WIND\_ALL= 3, 
208. 
209. Isp\_HorWndStart=0 
210. 
211. Isp\_HorWndLength=1280 
212. 
213. Isp\_VerWndStart=0 
214. 
215. Isp\_VerWndLength=720 
216. 
217. \[vb\_conf\] 
218. 
219. VbCnt=8 
220. 
221. 
222. \[venc\] 
223. 
224. RcMode =VENC\_RC\_MODE\_H264CBR 
225. 
226. Gop =30 
227. 
228. StatTime =1 
229. 
230. ViFrmRate =30 
231. 
232. TargetFrmRate=25 
233. ;----- only for VENC\_RC\_MODE\_H264CBR ---------- 
234. BitRate=4096 
235. FluctuateLevel=1 
236. ;----- only for VENC\_RC\_MODE\_H264VBR ---------- 
237. MaxBitRate =10000 
238. 
239. MaxQp=32 
240. 
241. MinQp=24 
242. ;----- only for VENC\_RC\_MODE\_H264FIXQP ---------- 
243. IQp=20 
244. 
245. PQp=23 
246. 
247. \[bind\] 
248. 
249. ViDev =0 
250. 
251. ViChn =0 
252. 
253. VpssGrp =0 
254. 
255. VpssChn = 0 
256. 
257. VencGrp =0 
258. 
259. VencChn =0 
260. 
261. VoDev =0 
262. 
263. VoChn =0 
264. 
265. ViSnapChn =0 
266. 
267. VpssSnapGrp=0 
268. 
269. VpssSnapChn=1 
270. 
271. VencSnapGrp=1 
272. 
273. VencSnapChn=1

[https_blog.csdn.net_dddxxxx_article_details_77451196]: https://blog.csdn.net/dddxxxx/article/details/77451196
[50040963]: /images/20220522/2490ad1ef4f64b36ba5638c712608362.png
[view plain]: /images/20220522/2490ad1ef4f64b36ba5638c712608362.png#