systemverilog FAQ(zz)

浅浅的花香味﹌ 2022-07-16 23:20 211阅读 0赞

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1. What is clocking block?

Ans: Clocking block can be declared using the keywords clocking and endclocking. A clocking block is mainly used in the testbench in order to avoid race conditions. Clocking blocks are used to assemble all the signals. They are useful in separating clocking activities from its main data activities. The declaration and instantiation of clocking block can both occur inside the module.

2. What are modports?

Ans: Modports define directions of ports as if they are declared inside the module. To restrict interface access within module modports are used. Modports can have inputs, outputs and inout ports also.

3. What are interfaces?

Ans: Interfaces enables the connectivity between the modules. It allows the smooth flow of design between the modules. The design can also be reused using interfaces. Using interfaces, we can replace a group of names with a single name which is helpful in reducing the size of program.

4. What are virtual interfaces? How can it be used?

Ans: A virtual interface can be used a reference to existing interface. It allows the subprogram to operate in parts of design.

5. What is a class?

Ans: Class is composed of set of members that describe how an instance of class or object is constructed and how it behaves.  
Eg: class class name\{  
member1;  
\---------------\}  
object name;

6. What is program block?

Ans: Program block is mainly used in thewriting of testbench. It is defined with a set of keywords, programand endprogram. It separates the testbenchfrom the device under test. This block works well in the hardwaredescription of the modules. Program block is also used to avoidrace conditions.

7. What is a mailbox?

Ans: Mailbox is communication mechanismthat allows the exchange of the messages between the processes.Mailboxes are helpful in the transmissionand receiving of the data in a systematic way.

8. What are semaphores?

Ans: A semaphore is like a bucket and usedin synchronization. They are inbuilt in systemveriolg. When asemaphore is allocated, the keys are allocatedto each and every bucket. The number is fixed. The keys are notidentical. Processes using semaphores must definitely have a keyfrom bucket before they start the execution process.

9. Why is reactive schedulerused?

Ans: Code specified in program blocks andpass/fail code from property expressions are scheduled in reactivescheduler.

10. What are rand and randc?

Ans: The variables in the class can bedeclared random using the keywords: rand and randc. Dynamic andassociative arrays can be declared using randor randc keywords.

11. What is the difference betweenkeywords: rand and randc?

Ans: Variables declared with rand keywordsare standard random variables. Their values are uniformlydistributed over their range. Values declaredwith randc keyword are randomly distributed. They are cyclic innature. They support only bit or enumerated data types. The size is limited.

12. What is the use ofalways\_ff?

Ans: The always\_ff can be used to modelsequential logic behavior. The always\_ff is alwayssynthesizable.

13. What are static and automaticfunctions?

Ans: For overriding the values in theclass, static function is used. Whereas in automatic, when one taskis called, two separate memories will beallocated.

14. What is the procedure to assignelements in an array in systemverilog?

Ans: Assigning arrays in systemveriloguses the replicate operators. Eg: intn\[1:2\]\[1:3\]=\{ \{0,1,2),\{3\{4\}\}\};

15. What are the types of arrays insystemverilog?

Ans: There are two terminologiesassociated with the arrays in systemverilog. Packed and unpackedarrays. When the dimensions of arrays are declaredbefore the object name is referred to as “packed arrays”. The“unpacked array” term is used to refer when the dimensions are declaredafter the object name. The memory allocation of both packed andunpacked arrays also differs.  
E.g.: int \[7:0\] c1; //packed array  
reg r\[7:0\] //unpacked array

16. What are assertions?

Ans: An assertion specifies a behavior ofthe system. They a re primarily used to validate a behavior ofdesign. Assertions can also be used to provide functional coverage and generate input stimulusfor validation.

17. What is the syntax for \#\# delay inassertion sequences?

Ans: Is called as cycle delay syntax: \#\#2; fifo.wdata < =8’hAA; //wait for 2 defaultclocking cycles, then drive wdata.

18. What are virtual classes?

Ans: When we use the same function name inboth the base and derived classes, the function in the base classis declared as virtual. The class is preceded using the keyword virtual before its normaldeclaration.

19. Why are assertions used?

Ans: Assertions are mainly used to checkthe behavior of the design whether it is working correctly or not.They are useful in providing the functionalcoverage information .i.e. how good the test is and whether thedesign meets all the requirements for testing. There are mainly twotypes of assertions in systemverilog. They are: immediateassertions and concurrent assertions.

20. Explain the difference between datatype’s logic and reg and wire.

Ans: Wire is basic data type which doesnot drive strength  
a) wire is used for designing combinationallogic. We can assign a single value to a wire by using the assignstatement. Wire cannot store any data.  
b) reg data type can be used for storage purpose. reg is used fordesigning both sequential and combinational circuits. reg datatypes can be driven from initial and always block .  
c) logic data types are similar to reg data types.

21. What is callback?

Ans: A callback is a built insystemverilog task/function. Suppose if we are transmitting a datausing mailbox and you are sending data from design to transmitter. If you want to get back the dataand you need the same data to put back in the scoreboard forcomparison, this is called callback. Any change in the transmitteddata can be achieved using the callback routine. Generallycallbacks are called bfore transmission and after receiving thedata.

22. What are the ways to avoid racecondition between testbench and RTL using SystemVerilog?

Ans: Using program block and clockingblock.

23. Explain event regions insystemverilog?

Ans: Active region: simulation of designcodes in modules.  
Observed region: checking the system verilogassertions.  
Reactive region: executing the testbench code.  
Postponed region: sampling the design signals for test benchinputs.

24. What are the types of coveragesavailable in systemverilog?

Ans: Functional coverage and codecoverage.

25. How can you detect a deadlockcondition in FSM?

Ans: It can be detected using a propertychecking with assertion.

26. What is mutex?

Ans: A Mutex object only allows one threadinto a controlled section. They cannot be executed by more than onethread in a concurrent manner. A mutex canbe released only through thread.

27. What is the significance of seed inrandomization?

Ans: If we want to produce the samesimulation results, seed is used. But the seed number should besame to perform the operation.

28. What is the difference between codecoverage and functional coverage?

Ans: Functional coverage: Functionalcoverage determines how much functionality of the design has beenexercised. Functional assertions are used tocheck whether each and every corner of the design is explored andfunctions properly. Code coverage: This will give information abouthow many lines are executed, how many times each expression isexecuted. It describes the level up to which the code has beentested.

29. If the functional coverage is morethat code coverage, what does it means?

Ans: code: High functional: High - You aremost likely done  
code: High functional: Low - Still need torun more simulation or improve test bench  
code: Low functional: High - Probably missing functional coveragepoints  
code: Low functional: Low - Still need to run more simulation orimprove test bench

30. How we can have \#delay which isindependent of time scale in system verilog?

Ans: We can mention it as \#5ns.

31. What are constraints insystemverilog?

Ans: By specifying constraints, users caneasily create tests that are very difficult to reach corners of thedesign. Sytemverilog allows users to specifyconstraints in compact and declarative way. Random values aregenerated to meet the constraints.

32. What are the different types ofconstraints in systemverilog?

Ans: Random constraints, user definedconstraints, inline constraints, if-else constraints and globalconstraints.

33. What is an if-elseconstraint?

Ans: If the given expression is true, allthe constraints in the first constraint block should be satisfied,otherwise all of the constraints in the elseconstraint block will be satisfied.

34. What is inheritance and give the basicsyntax for it?

Ans: A derived class by default has theproperties and methods of the base class or parent class. This iscalled inheritance.  
Syntax: class Derived extendsBaseClass;  
// method declarations.  
endclass

35. What is the difference between programblock and module?

Ans: The module is the basic buildingblock in verilog which is used in creating a design. Systemverilogadds a new block called program block whichcan be declared using the keywords program and endprogram. Theprogram block separates the design and testbench. The program blockand module differs in syntax also.

36. What is final block?

Ans: Systemverilog adds a final block thatexecutes the end of simulation. There is nothing to be executedafter the final block. It is the end of simulation. Final block should not have anydelays.

37. What are dynamic and associativearrays?

Ans: When array is declared, memory isallocated for the elements of array when the program starts. Memoryis allocated to the array only when thearrays are declared in the program. The memory remains allocatedduring the lifetime of the program. This is called static array. Itmay sometimes happen that we don’t know how large an array we willneed. In this case, it is convenient to allocate an array while theprogram is running. This is called dynamic array. Dynamic array isa one dimensional array.

38. What is an abstract class?

Ans: Abstract classes are those which canbe used for creation of handles. Their methods and constructors andcan be used by the class or extended class.They are used to generalize the super class from which childclasses can share its methods.

39. What is the difference between $randomand $urandom?

Ans: $random and $random are both systemfunctions.  
1. $random returns a 32-bit signed randomnumber whenever it is added.  
2. $urandom returns a 32-bit unsigned random number whenever it isadded. It a newly added system function insystemverilog.

40. What is the use of $cast?

Ans: Systemverilog provides $cast systemtask to assign values to variables that may not be valid because ofdiffering data type. $cast can be called aseither a task or a function. $cast is basically used in dynamiccasting. For more accurate checking of values, $cast is used.  
Syntax: $cast(des\_val, eval\_expr)

41. What is the difference between mailboxand queue?

Ans: Mailbox is similar to a queue, whichallows only atomic operations. They can be bounded/unbounded.Get/put task is used to suspend a boundedmailbox. That’s why mailbox is used more for communication betweenthreads. Queues are large structures. Inserting data in queues isvery difficult.

42. What are bidirectionalconstraints?

Ans: Constraints in systemverilog arebidirectional by default. That means they do not follow anysequence in which the constraints are mentioned. All the variables are lookedsimultaneously.

43. What is circular dependency and how toavoid this problem?

Ans: Over specifying the solving ordermight result in circular dependency. There is no solution forcircular dependency. The constraint solver might give error/warning or noconstraining.

44. What is the significance of superkeyword?

Ans: The super keyword is used from thederived class to refer to the members of the derived class. If wewant to access members of derived class thatare overridden by the derived class, super keyword is used. Superkeyword cannot be accessed directly.

45. What is the significance of thiskeyword?

Ans: This keyword is used to call theparameters of same class.

46. What are input and output skews inclocking block?

Ans: Skews are numbers that are indicatedbefore the input and output ports. A skew number indicated beforean input defines that the input is sampledbefore the clocking event occurs, ie a posedge or negedge occurs. Askew number in the output indicates that the output is synchronizedand then sent to the clocking blocks. A skew must be a constantexpression. It can also be specified as aparameter.

47. What is a scoreboard?

Ans: Dynamic data types and dynamic memoryallocations in systemverilog makes us easy to write scoreboards.Scoreboard is used to store the expectedoutput of the device under test. It implements the samefunctionality as DUT. It uses higher level ofconstructs.

48. Mention the purpose of dividing timeslots in systemverilog?

Ans: The main purpose of dividing the timeslots in systemverilog is to provide interaction between the designand the testbench.

49. What is static variable?

Ans: In systemverilog we can create astatic variable inside the class. But this variable has a limitedscope. The variable declared static is shared among the other variables in the class. A staticvariable is usually instantiated inside thedeclaration.

50. In simulation environment under whatcondition the simulation should end?

Ans: 1) Packet count match  
2) Error  
3) Error count  
4) Interface idle count  
5) Global Time out

51. What is public declaration?

Ans: Objects in systemverilog can bedeclared as public and private. Public declarations are accessiblefrom outside that object, i.e. they are accessible by the users. By default declarations insystemverilog are public.

52. What is the use of local?

Ans: In order to make the declarationsprivate, local attribute is used. Once the data is declared aslocal, it can be accessed on in the particular class.