Non-uniform memory access

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# Non-uniform memory access #

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**Non-uniform memory access** (**NUMA**) is a [ computer memory][computer memory] design used in [ multiprocessing][multiprocessing], where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors). The benefits of NUMA are limited to particular workloads, notably on servers where the data are often associated strongly with certain tasks or users.[\[1\]][1]

NUMA architectures logically follow in scaling from [ symmetric multiprocessing][symmetric multiprocessing] (SMP) architectures. They were developed commercially during the 1990s by [ Burroughs][Burroughs] (later [ Unisys][Unisys]), [ Convex Computer][Convex Computer] (later [ Hewlett-Packard][Hewlett-Packard]), [ Honeywell][Honeywell] Information Systems Italy (HISI) (later [ Groupe Bull][Groupe Bull]), [ Silicon Graphics][Silicon Graphics] (later [ Silicon Graphics International][Silicon Graphics International]), [ Sequent Computer Systems][Sequent Computer Systems] (later [ IBM][IBM]), [ Data General][Data General] (later [ EMC][EMC]), and [ Digital][Digital] (later [ Compaq][Compaq], now [ HP][HP]). Techniques developed by these companies later featured in a variety of [ Unix-like][Unix-like] [ operating systems][operating systems], and to an extent in [ Windows NT][Windows NT].

The first commercial implementation of a NUMA-based Unix system was the Symmetrical Multi Processing XPS-100 family of servers, designed by Dan Gielan of VAST Corporation for Honeywell Information Systems Italy.

## Contents ##

\[[hide][]\]

*  [1 Basic concept][]
 *  [2 Cache coherent NUMA (ccNUMA)][2 Cache coherent NUMA _ccNUMA]
 *  [3 NUMA vs. cluster computing][]
 *  [4 Software support][]
 *  [5 See also][]
 *  [6 References][]
 *  [7 External links][]

## Basic concept\[[edit][]\] ##

[![300px-NUMA.svg.png][]][300px-NUMA.svg.png 1]

[![magnify-clip.png][]][300px-NUMA.svg.png 1]

One possible architecture of a NUMA system. The processors connect to the bus or crossbar by connections of varying thickness/number. This shows that different CPUs have different access priorities to memory based on their relative location.

Modern CPUs operate considerably faster than the main memory they use. In the early days of computing and data processing, the CPU generally ran slower than its own memory. The performance lines of processors and memory crossed in the 1960s with the advent of the first supercomputers. Since then, CPUs increasingly have found themselves "starved for data" and having to stall while waiting for data to arrive from memory. Many supercomputer designs of the 1980s and 1990s focused on providing high-speed memory access as opposed to faster processors, allowing the computers to work on large data sets at speeds other systems could not approach.

Limiting the number of memory accesses provided the key to extracting high performance from a modern computer. For commodity processors, this meant installing an ever-increasing amount of high-speed [ cache memory][cache memory] and using increasingly sophisticated algorithms to avoid [ cache misses][cache misses]. But the dramatic increase in size of the operating systems and of the applications run on them has generally overwhelmed these cache-processing improvements. Multi-processor systems without NUMA make the problem considerably worse. Now a system can starve several processors at the same time, notably because only one processor can access the computer's memory at a time.[\[2\]][2]

NUMA attempts to address this problem by providing separate memory for each processor, avoiding the performance hit when several processors attempt to address the same memory. For problems involving spread data (common for [ servers][servers] and similar applications), NUMA can improve the performance over a single shared memory by a factor of roughly the number of processors (or separate memory banks).[\[3\]][3] Another approach to addressing this problem, utilized mainly by non-NUMA systems, is the [ multi-channel memory architecture][multi-channel memory architecture]; multiple memory channels are increasing the number of simultaneous memory accesses.[\[4\]][4]

Of course, not all data ends up confined to a single task, which means that more than one processor may require the same data. To handle these cases, NUMA systems include additional hardware or software to move data between memory banks. This operation slows the processors attached to those banks, so the overall speed increase due to NUMA depends heavily on the nature of the running tasks.[\[3\]][3]

Intel announced NUMA compatibility for its x86 and Itanium servers in late 2007 with its [ Nehalem][Nehalem] and [ Tukwila][Tukwila] CPUs.[\[5\]][5] Both CPU families share a common [chipset][]; the interconnection is called Intel [ Quick Path Interconnect][Quick Path Interconnect] (QPI).[\[6\]][6] AMD implemented NUMA with its [Opteron][] processor (2003), using [ HyperTransport][HyperTransport]. Freescale's NUMA for PowerPC is called CoreNet.

## Cache coherent NUMA (ccNUMA)\[[edit][edit 1]\] ##

[![300px-Hwloc.png][]][300px-Hwloc.png 1]

[![magnify-clip.png][]][300px-Hwloc.png 1]

Topology of a ccNUMA [ Bulldozer][Bulldozer] server.

Nearly all CPU architectures use a small amount of very fast non-shared memory known as [ cache][cache] to exploit [ locality of reference][locality of reference] in memory accesses. With NUMA, maintaining [ cache coherence][cache coherence] across shared memory has a significant overhead. Although simpler to design and build, non-cache-coherent NUMA systems become prohibitively complex to program in the standard [ von Neumann architecture][von Neumann architecture] programming model.[\[7\]][7]

Typically, ccNUMA uses inter-processor communication between cache controllers to keep a consistent memory image when more than one cache stores the same memory location. For this reason, ccNUMA may perform poorly when multiple processors attempt to access the same memory area in rapid succession. Support for NUMA in [ operating systems][operating systems] attempts to reduce the frequency of this kind of access by allocating processors and memory in NUMA-friendly ways and by avoiding scheduling and locking algorithms that make NUMA-unfriendly accesses necessary.[\[8\]][8]

Alternatively, cache coherency protocols such as the [ MESIF protocol][MESIF protocol] attempt to reduce the communication required to maintain cache coherency. [ Scalable Coherent Interface][Scalable Coherent Interface] (SCI) is an [ IEEE][IEEE] standard defining a directory-based cache coherency protocol to avoid scalability limitations found in earlier multiprocessor systems. For example, SCI is used as the basis for the NumaConnect technology.[\[9\]][9][\[10\]][10]

As of 2011, ccNUMA systems are multiprocessor systems based on the [ AMD Opteron][AMD Opteron] processor, which can be implemented without external logic, and the [ Intel][Intel] [ Itanium][Itanium] processor, which requires the chipset to support NUMA. Examples of ccNUMA-enabled chipsets are the SGI Shub (Super hub), the Intel E8870, the [ HP][HP 1] sx2000 (used in the Integrity and Superdome servers), and those found in NEC Itanium-based systems. Earlier ccNUMA systems such as those from [ Silicon Graphics][Silicon Graphics] were based on [ MIPS][MIPS] processors and the [ DEC][Digital] [ Alpha 21364][Alpha 21364] (EV7) processor.

## NUMA vs. cluster computing\[[edit][edit 2]\] ##

One can view NUMA as a tightly coupled form of [ cluster computing][cluster computing]. The addition of [ virtual memory][virtual memory] paging to a cluster architecture can allow the implementation of NUMA entirely in software. However, the inter-node latency of software-based NUMA remains several orders of magnitude greater (slower) than that of hardware-based NUMA.[\[1\]][1]

## Software support\[[edit][edit 3]\] ##

Since NUMA largely influences memory access performance, certain software optimizations are needed to allow scheduling threads and processes close to their data.

*  [Microsoft][] [ Windows 7][Windows 7] and [ Windows Server 2008 R2][Windows Server 2008 R2] add support for NUMA architecture over 64 logical cores.[\[11\]][11]
 *  [Java 7][] added support for NUMA-aware memory allocator and [ garbage collector][garbage collector].[\[12\]][12]
 *  The [ Linux kernel][Linux kernel] 2.5 already had basic support built-in,[\[13\]][13] which was further extended in subsequent releases. Linux kernel version 3.8 brought a new NUMA foundation which allowed more efficient NUMA policies to be built in the next kernel releases.[\[14\]][14][\[15\]][15] Linux kernel version 3.13 brought numerous policies that attempt to put a process near its memory, together with handling of cases such as shared pages between processes, or transparent [ huge pages][huge pages]; new [ sysctl][sysctl] settings are allowing NUMA balancing to be enabled or disabled, as well as various NUMA memory balancing parameters to be configured.[\[16\]][16][\[17\]][17][\[18\]][18]
 *  [OpenSolaris][] models NUMA architecture with lgroups.

## See also\[[edit][edit 4]\] ##

*  [Uniform memory access][] (UMA)
 *  [Cluster computing][cluster computing]
 *  [Symmetric multiprocessing][symmetric multiprocessing] (SMP)
 *  [Cache only memory architecture][] (COMA)
 *  [Scratchpad memory][] (SPM)
 *  [Supercomputer][]
 *  [Silicon Graphics][] (SGI)
 *  [HiperDispatch][]
 *  [Intel QuickPath Interconnect (QPI)][Quick Path Interconnect]
 *  [HyperTransport][]

## References\[[edit][edit 5]\] ##

1.  ^ [ Jump up to: ***a***][Jump up to_ _a] [ ***b***][_b] Nakul Manchanda; Karan Anand (2010-05-04). [ "Non-Uniform Memory Access (NUMA)"][_Non-Uniform Memory Access _NUMA]. New York University. Retrieved 2014-01-27. 
2.  **[Jump up ^][Jump up]** Sergey Blagodurov; Sergey Zhuravlev; Mohammad Dashti; Alexandra Fedorov (2011-05-02). [ "A Case for NUMA-aware Contention Management on Multicore Systems"][_A Case for NUMA-aware Contention Management on Multicore Systems] (PDF). Simon Fraser University. Retrieved 2014-01-27. 
3.  ^ [ Jump up to: ***a***][Jump up to_ _a 1] [ ***b***][_b 1] Zoltan Majo; Thomas R. Gross (2011). [ "Memory System Performance in a NUMA Multicore Multiprocessor"][_Memory System Performance in a NUMA Multicore Multiprocessor] (PDF). ACM. Retrieved 2014-01-27. 
4.  **[Jump up ^][Jump up 1]** ["Intel Dual-Channel DDR Memory Architecture White Paper"][Intel Dual-Channel DDR Memory Architecture White Paper] (PDF, 1021 [KB][]) (Rev. 1.0 ed.). Infineon Technologies North America and Kingston Technology. September 2003. Archived from [ the original][the original] on 2011-09-29. Retrieved 2007-09-06. 
5.  **[Jump up ^][Jump up 2]** Intel Corp. (2008). Intel QuickPath Architecture \[White paper\]. Retrieved from [ http://www.intel.com/pressroom/archive/reference/whitepaper\_QuickPath.pdf][http_www.intel.com_pressroom_archive_reference_whitepaper_QuickPath.pdf]
6.  **[Jump up ^][Jump up 3]** Intel Corporation. (September 18th, 2007). Gelsinger Speaks To Intel And High-Tech Industry's Rapid Technology Caden\[Press release\]. Retrieved from [ http://www.intel.com/pressroom/archive/releases/2007/20070918corp\_b.htm][http_www.intel.com_pressroom_archive_releases_2007_20070918corp_b.htm]
7.  **[Jump up ^][Jump up 4]** ["ccNUMA: Cache Coherent Non-Uniform Memory Access"][ccNUMA_ Cache Coherent Non-Uniform Memory Access]. slideshare.net. 2014. Retrieved 2014-01-27. 
8.  **[Jump up ^][Jump up 5]** Per Stenstromt; Truman Joe; Anoop Gupta (2002). [ "Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures"][_Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures] (PDF). ACM. Retrieved 2014-01-27. 
9.  **[Jump up ^][Jump up 6]** David B. Gustavson (September 1991). [ "The Scalable Coherent Interface and Related Standards Projects"][_The Scalable Coherent Interface and Related Standards Projects]. *SLAC Publication 5656*. [ Stanford Linear Accelerator Center][Stanford Linear Accelerator Center]. Retrieved January 27, 2014. 
10. **[Jump up ^][Jump up 7]** ["The NumaChip enables cache coherent low cost shared memory"][The NumaChip enables cache coherent low cost shared memory]. Numascale.com. Retrieved 2014-01-27. 
11. **[Jump up ^][Jump up 8]** [NUMA Support (MSDN)][NUMA Support _MSDN]
12. **[Jump up ^][Jump up 9]** [Java HotSpot™ Virtual Machine Performance Enhancements][Java HotSpot_ Virtual Machine Performance Enhancements]
13. **[Jump up ^][Jump up 10]** ["Linux Scalability Effort: NUMA Group Homepage"][Linux Scalability Effort_ NUMA Group Homepage]. sourceforge.net. 2002-11-20. Retrieved 2014-02-06. 
14. **[Jump up ^][Jump up 11]** ["1.8. Automatic NUMA balancing"][1.8. Automatic NUMA balancing]. *Linux 3.8*. kernelnewbies.org. 2013-02-08. Retrieved 2014-02-06. 
15. **[Jump up ^][Jump up 12]** Jonathan Corbet (2012-11-14). [ "NUMA in a hurry"][_NUMA in a hurry]. [ LWN.net][LWN.net]. Retrieved 2014-02-06. 
16. **[Jump up ^][Jump up 13]** ["1.6. Improved performance in NUMA systems"][1.6. Improved performance in NUMA systems]. *Linux 3.13*. kernelnewbies.org. 2014-01-19. Retrieved 2014-02-06. 
17. **[Jump up ^][Jump up 14]** ["Documentation/sysctl/kernel.txt"][Documentation_sysctl_kernel.txt]. *Linux kernel documentation*. kernel.org. Retrieved 2014-02-06. 
18. **[Jump up ^][Jump up 15]** Jonathan Corbet (2013-10-01). [ "NUMA scheduling progress"][_NUMA scheduling progress]. [ LWN.net][LWN.net]. Retrieved 2014-02-06.

This article is based on material taken from the [ Free On-line Dictionary of Computing][Free On-line Dictionary of Computing] prior to 1 November 2008 and incorporated under the "relicensing" terms of the [ GFDL][GFDL], version 1.3 or later.

## External links\[[edit][edit 6]\] ##

*  [NUMA FAQ][]
 *  [Page-based distributed shared memory][]
 *  [OpenSolaris NUMA Project][]
 *  [Introduction video for the Alpha EV7 system architecture][]
 *  [More videos related to EV7 systems: CPU, IO, etc][More videos related to EV7 systems_ CPU_ IO_ etc]
 *  [NUMA optimization in Windows Applications][]
 *  [NUMA Support in Linux at SGI][]
 *  [Intel Tukwila][]
 *  [Intel QPI (CSI) explained][Intel QPI _CSI_ explained]
 *  [current Itanium NUMA systems][]

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       <td colspan="2">&nbsp;</td> 
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       <th>Levels</th> 
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         <ul> 
          <li><a title="Bit-level parallelism" href="http://en.wikipedia.org/wiki/Bit-level_parallelism" rel="nofollow">Bit</a> </li> 
          <li><a title="Instruction-level parallelism" href="http://en.wikipedia.org/wiki/Instruction-level_parallelism" rel="nofollow">Instruction</a> </li> 
          <li><a title="Data parallelism" href="http://en.wikipedia.org/wiki/Data_parallelism" rel="nofollow">Data</a> </li> 
          <li><a title="Task parallelism" href="http://en.wikipedia.org/wiki/Task_parallelism" rel="nofollow">Task</a> </li> 
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       <th><a title="Multithreading (computer architecture)" href="http://en.wikipedia.org/wiki/Multithreading_%28computer_architecture%29" rel="nofollow">Multithreading</a></th> 
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         <ul> 
          <li><a title="Temporal multithreading" href="http://en.wikipedia.org/wiki/Temporal_multithreading" rel="nofollow">Temporal multithreading</a> </li> 
          <li><a title="Simultaneous multithreading" href="http://en.wikipedia.org/wiki/Simultaneous_multithreading" rel="nofollow">Simultaneous multithreading</a> 
           <ul> 
            <li><a title="Hyper-threading" href="http://en.wikipedia.org/wiki/Hyper-threading" rel="nofollow">Hyper-threading</a> </li> 
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       <th>Theory</th> 
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         <ul> 
          <li><a title="Amdahl's law" href="http://en.wikipedia.org/wiki/Amdahl%27s_law" rel="nofollow">Amdahl's law</a> </li> 
          <li><a title="Gustafson's law" href="http://en.wikipedia.org/wiki/Gustafson%27s_law" rel="nofollow">Gustafson's law</a> </li> 
          <li><a title="Cost efficiency" href="http://en.wikipedia.org/wiki/Cost_efficiency" rel="nofollow">Cost efficiency</a> </li> 
          <li><a title="Karp–Flatt metric" href="http://en.wikipedia.org/wiki/Karp%E2%80%93Flatt_metric" rel="nofollow">Karp–Flatt metric</a> </li> 
          <li><a title="Parallel slowdown" href="http://en.wikipedia.org/wiki/Parallel_slowdown" rel="nofollow">slowdown</a> </li> 
          <li><a title="Speedup" href="http://en.wikipedia.org/wiki/Speedup" rel="nofollow">speedup</a> </li> 
         </ul> 
        </div> </td> 
      </tr> 
      <tr style="height:2px"> 
       <td colspan="2">&nbsp;</td> 
      </tr> 
      <tr> 
       <th>Elements</th> 
       <td style="padding:0px; width:100%; border-left-width:2px; border-left-style:solid"> 
        <div style="padding:0em 0.25em"> 
         <ul> 
          <li><a title="Process (computing)" href="http://en.wikipedia.org/wiki/Process_%28computing%29" rel="nofollow">Process</a> </li> 
          <li><a title="Thread (computing)" href="http://en.wikipedia.org/wiki/Thread_%28computing%29" rel="nofollow">Thread</a> </li> 
          <li><a title="Fiber (computer science)" href="http://en.wikipedia.org/wiki/Fiber_%28computer_science%29" rel="nofollow">Fiber</a> </li> 
          <li><a title="Parallel random-access machine" href="http://en.wikipedia.org/wiki/Parallel_random-access_machine" rel="nofollow">PRAM</a> </li> 
          <li><a title="Instruction window" href="http://en.wikipedia.org/wiki/Instruction_window" rel="nofollow">Instruction window</a> </li> 
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       <th>Coordination</th> 
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          <li><a title="Multiprocessing" href="http://en.wikipedia.org/wiki/Multiprocessing" rel="nofollow">Multiprocessing</a> </li> 
          <li><a title="Memory coherence" href="http://en.wikipedia.org/wiki/Memory_coherence" rel="nofollow">Memory coherency</a> </li> 
          <li><a title="Cache coherence" href="http://en.wikipedia.org/wiki/Cache_coherence" rel="nofollow">Cache coherency</a> </li> 
          <li><a title="Cache invalidation" href="http://en.wikipedia.org/wiki/Cache_invalidation" rel="nofollow">Cache invalidation</a> </li> 
          <li><a title="Barrier (computer science)" href="http://en.wikipedia.org/wiki/Barrier_%28computer_science%29" rel="nofollow">Barrier</a> </li> 
          <li><a title="Synchronization (computer science)" href="http://en.wikipedia.org/wiki/Synchronization_%28computer_science%29" rel="nofollow">Synchronization</a> </li> 
          <li><a title="Application checkpointing" href="http://en.wikipedia.org/wiki/Application_checkpointing" rel="nofollow">Application checkpointing</a> </li> 
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          <li><a title="Parallel programming model" href="http://en.wikipedia.org/wiki/Parallel_programming_model" rel="nofollow">Models</a> 
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            <li><a title="Implicit parallelism" href="http://en.wikipedia.org/wiki/Implicit_parallelism" rel="nofollow">Implicit parallelism</a> </li> 
            <li><a title="Explicit parallelism" href="http://en.wikipedia.org/wiki/Explicit_parallelism" rel="nofollow">Explicit parallelism</a> </li> 
            <li><a title="Concurrency (computer science)" href="http://en.wikipedia.org/wiki/Concurrency_%28computer_science%29" rel="nofollow">Concurrency</a> </li> 
           </ul> </li> 
          <li><a title="Flynn's taxonomy" href="http://en.wikipedia.org/wiki/Flynn%27s_taxonomy" rel="nofollow">Flynn's taxonomy</a> 
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            <li><a title="SISD" href="http://en.wikipedia.org/wiki/SISD" rel="nofollow">SISD</a> </li> 
            <li><a title="SIMD" href="http://en.wikipedia.org/wiki/SIMD" rel="nofollow">SIMD</a> </li> 
            <li><a title="MISD" href="http://en.wikipedia.org/wiki/MISD" rel="nofollow">MISD</a> </li> 
            <li><a title="MIMD" href="http://en.wikipedia.org/wiki/MIMD" rel="nofollow">MIMD</a> 
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              <li><a title="SPMD" href="http://en.wikipedia.org/wiki/SPMD" rel="nofollow">SPMD</a> </li> 
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           </ul> </li> 
          <li><a title="Thread (computing)" href="http://en.wikipedia.org/wiki/Thread_%28computing%29" rel="nofollow">Thread</a> </li> 
          <li><a title="Non-blocking algorithm" href="http://en.wikipedia.org/wiki/Non-blocking_algorithm" rel="nofollow">Non-blocking algorithm</a> </li> 
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       <th><a title="Computer hardware" href="http://en.wikipedia.org/wiki/Computer_hardware" rel="nofollow">Hardware</a></th> 
       <td style="padding:0px; width:100%; border-left-width:2px; border-left-style:solid"> 
        <div style="padding:0em 0.25em"> 
         <ul> 
          <li><a title="Multiprocessor" href="http://en.wikipedia.org/wiki/Multiprocessor" rel="nofollow">Multiprocessor</a> 
           <ul> 
            <li><a title="Symmetric multiprocessing" href="http://en.wikipedia.org/wiki/Symmetric_multiprocessing" rel="nofollow">Symmetric</a> </li> 
            <li><a title="Asymmetric multiprocessing" href="http://en.wikipedia.org/wiki/Asymmetric_multiprocessing" rel="nofollow">Asymmetric</a> </li> 
           </ul> </li> 
          <li><a title="Semiconductor memory" href="http://en.wikipedia.org/wiki/Semiconductor_memory" rel="nofollow">Memory</a> 
           <ul> 
            <li><span style="font-weight:bold">NUMA</span> </li> 
            <li><a title="Cache-only memory architecture" href="http://en.wikipedia.org/wiki/Cache-only_memory_architecture" rel="nofollow">COMA</a> </li> 
            <li><a title="Distributed memory" href="http://en.wikipedia.org/wiki/Distributed_memory" rel="nofollow">distributed</a> </li> 
            <li><a title="Shared memory" href="http://en.wikipedia.org/wiki/Shared_memory" rel="nofollow">shared</a> </li> 
            <li><a title="Distributed shared memory" href="http://en.wikipedia.org/wiki/Distributed_shared_memory" rel="nofollow">distributed shared</a> </li> 
           </ul> </li> 
          <li><a title="Massively parallel (computing)" href="http://en.wikipedia.org/wiki/Massively_parallel_%28computing%29" rel="nofollow">MPP</a> </li> 
          <li><a title="Superscalar" href="http://en.wikipedia.org/wiki/Superscalar" rel="nofollow">Superscalar</a> </li> 
          <li><a title="Vector processor" href="http://en.wikipedia.org/wiki/Vector_processor" rel="nofollow">Vector processor</a> </li> 
          <li><a title="Supercomputer" href="http://en.wikipedia.org/wiki/Supercomputer" rel="nofollow">Supercomputer</a> </li> 
          <li><a title="Beowulf cluster" href="http://en.wikipedia.org/wiki/Beowulf_cluster" rel="nofollow">Beowulf cluster</a> </li> 
         </ul> 
        </div> </td> 
      </tr> 
      <tr style="height:2px"> 
       <td colspan="2">&nbsp;</td> 
      </tr> 
      <tr> 
       <th><a title="Application programming interface" href="http://en.wikipedia.org/wiki/Application_programming_interface" rel="nofollow">APIs</a></th> 
       <td style="padding:0px; width:100%; border-left-width:2px; border-left-style:solid"> 
        <div style="padding:0em 0.25em"> 
         <ul> 
          <li><a title="Ateji PX" href="http://en.wikipedia.org/wiki/Ateji_PX" rel="nofollow">Ateji PX</a> </li> 
          <li><a title="POSIX Threads" href="http://en.wikipedia.org/wiki/POSIX_Threads" rel="nofollow">POSIX Threads</a> </li> 
          <li><a title="OpenMP" href="http://en.wikipedia.org/wiki/OpenMP" rel="nofollow">OpenMP</a> </li> 
          <li><a title="OpenHMPP" href="http://en.wikipedia.org/wiki/OpenHMPP" rel="nofollow">OpenHMPP</a> </li> 
          <li><a title="OpenACC" href="http://en.wikipedia.org/wiki/OpenACC" rel="nofollow">OpenACC</a> </li> 
          <li><a title="Parallel Virtual Machine" href="http://en.wikipedia.org/wiki/Parallel_Virtual_Machine" rel="nofollow">PVM</a> </li> 
          <li><a title="Message Passing Interface" href="http://en.wikipedia.org/wiki/Message_Passing_Interface" rel="nofollow">MPI</a> </li> 
          <li><a title="Unified Parallel C" href="http://en.wikipedia.org/wiki/Unified_Parallel_C" rel="nofollow">UPC</a> </li> 
          <li><a title="Threading Building Blocks" href="http://en.wikipedia.org/wiki/Threading_Building_Blocks" rel="nofollow">TBB</a> </li> 
          <li><a title="Boost (C++ libraries)" href="http://en.wikipedia.org/wiki/Boost_%28C%2B%2B_libraries%29#Multithreading_.E2.80.93_Boost.Thread" rel="nofollow">Boost.Thread</a> </li> 
          <li><a title="Global Arrays" href="http://en.wikipedia.org/wiki/Global_Arrays" rel="nofollow">Global Arrays</a> </li> 
          <li><a title="Charm++" href="http://en.wikipedia.org/wiki/Charm%2B%2B" rel="nofollow">Charm++</a> </li> 
          <li><a title="Cilk" href="http://en.wikipedia.org/wiki/Cilk" rel="nofollow">Cilk</a>/<a title="Cilk Plus" href="http://en.wikipedia.org/wiki/Cilk_Plus" rel="nofollow">Cilk Plus</a> </li> 
          <li><a title="Coarray Fortran" href="http://en.wikipedia.org/wiki/Coarray_Fortran" rel="nofollow">Coarray Fortran</a> </li> 
          <li><a title="OpenCL" href="http://en.wikipedia.org/wiki/OpenCL" rel="nofollow">OpenCL</a> </li> 
          <li><a title="CUDA" href="http://en.wikipedia.org/wiki/CUDA" rel="nofollow">CUDA</a> </li> 
          <li><a title="Dryad (programming)" href="http://en.wikipedia.org/wiki/Dryad_%28programming%29" rel="nofollow">Dryad</a> </li> 
          <li><a title="C++ AMP" href="http://en.wikipedia.org/wiki/C%2B%2B_AMP" rel="nofollow">C++ AMP</a> </li> 
          <li><a title="Parallel LINQ" href="http://en.wikipedia.org/wiki/Parallel_LINQ" rel="nofollow">PLINQ</a> </li> 
          <li><a title="Parallel Extensions" href="http://en.wikipedia.org/wiki/Parallel_Extensions#Task_Parallel_Library" rel="nofollow">TPL</a> </li> 
         </ul> 
        </div> </td> 
      </tr> 
      <tr style="height:2px"> 
       <td colspan="2">&nbsp;</td> 
      </tr> 
      <tr> 
       <th>Problems</th> 
       <td style="padding:0px; width:100%; border-left-width:2px; border-left-style:solid"> 
        <div style="padding:0em 0.25em"> 
         <ul> 
          <li><a title="Embarrassingly parallel" href="http://en.wikipedia.org/wiki/Embarrassingly_parallel" rel="nofollow">Embarrassingly parallel</a> </li> 
          <li><a title="Software lockout" href="http://en.wikipedia.org/wiki/Software_lockout" rel="nofollow">Software lockout</a> </li> 
          <li><a title="Scalability" href="http://en.wikipedia.org/wiki/Scalability" rel="nofollow">Scalability</a> </li> 
          <li><a title="Race condition" href="http://en.wikipedia.org/wiki/Race_condition#Computing" rel="nofollow">Race condition</a> </li> 
          <li><a title="Deadlock" href="http://en.wikipedia.org/wiki/Deadlock" rel="nofollow">Deadlock</a> </li> 
          <li><a title="Deadlock" href="http://en.wikipedia.org/wiki/Deadlock#Livelock" rel="nofollow">Livelock</a> </li> 
          <li><a title="Resource starvation" href="http://en.wikipedia.org/wiki/Resource_starvation" rel="nofollow">Starvation</a> </li> 
          <li><a title="Deterministic algorithm" href="http://en.wikipedia.org/wiki/Deterministic_algorithm" rel="nofollow">Deterministic algorithm</a> </li> 
          <li><a title="Parallel slowdown" href="http://en.wikipedia.org/wiki/Parallel_slowdown" rel="nofollow">Parallel slowdown</a> </li> 
         </ul> 
        </div> </td> 
      </tr> 
      <tr style="height:2px"> 
       <td colspan="2">&nbsp;</td> 
      </tr> 
      <tr> 
       <td colspan="2"> 
        <ul> 
         <li><img width="16" height="14" alt="Category" src="http://upload.wikimedia.org/wikipedia/en/thumb/4/48/Folder_Hexagonal_Icon.svg/16px-Folder_Hexagonal_Icon.svg.png">&nbsp;<a title="Category:Parallel computing" href="http://en.wikipedia.org/wiki/Category:Parallel_computing" rel="nofollow">Category: parallel computing</a> </li> 
         <li><img width="12" height="16" alt="" src="http://upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/12px-Commons-logo.svg.png"> Media related to <a title="commons:Category:parallel computing" href="http://commons.wikimedia.org/wiki/Category:parallel_computing" rel="nofollow"> parallel computing</a> at Wikimedia Commons </li> 
        </ul> </td> 
      </tr> 
     </tbody> 
    </table> </td> 
  </tr> 
 </tbody> 
</table>

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[Categories][]:

*  [Parallel computing][]
 *  [Computer memory][]

注：近期参加MySQL运维学习，老师推荐该文章作为学习和技术提高的扩展阅读，先记录到自己的博客中，随后慢慢消化、学习、提高。本文与MySQL数据库 “性能优化”主题有关。

[Non-Uniform Memory Access]: http://en.wikipedia.org/w/index.php?title=Non-Uniform_Memory_Access&redirect=no
[navigation]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#mw-navigation
[search]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#p-search
[computer memory]: http://en.wikipedia.org/wiki/Computer_storage
[multiprocessing]: http://en.wikipedia.org/wiki/Multiprocessing
[1]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-nyu-numa-1
[symmetric multiprocessing]: http://en.wikipedia.org/wiki/Symmetric_multiprocessing
[Burroughs]: http://en.wikipedia.org/wiki/Burroughs_large_systems
[Unisys]: http://en.wikipedia.org/wiki/Unisys
[Convex Computer]: http://en.wikipedia.org/wiki/Convex_Computer
[Hewlett-Packard]: http://en.wikipedia.org/wiki/Hewlett-Packard
[Honeywell]: http://en.wikipedia.org/wiki/Honeywell
[Groupe Bull]: http://en.wikipedia.org/wiki/Groupe_Bull
[Silicon Graphics]: http://en.wikipedia.org/wiki/Silicon_Graphics
[Silicon Graphics International]: http://en.wikipedia.org/wiki/Silicon_Graphics_International
[Sequent Computer Systems]: http://en.wikipedia.org/wiki/Sequent_Computer_Systems
[IBM]: http://en.wikipedia.org/wiki/IBM
[Data General]: http://en.wikipedia.org/wiki/Data_General
[EMC]: http://en.wikipedia.org/wiki/EMC_Corporation
[Digital]: http://en.wikipedia.org/wiki/Digital_Equipment_Corporation
[Compaq]: http://en.wikipedia.org/wiki/Compaq
[HP]: http://en.wikipedia.org/wiki/HP
[Unix-like]: http://en.wikipedia.org/wiki/Unix-like
[operating systems]: http://en.wikipedia.org/wiki/Operating_system
[Windows NT]: http://en.wikipedia.org/wiki/Windows_NT
[hide]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#
[1 Basic concept]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#Basic_concept
[2 Cache coherent NUMA _ccNUMA]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#Cache_coherent_NUMA_.28ccNUMA.29
[3 NUMA vs. cluster computing]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#NUMA_vs._cluster_computing
[4 Software support]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#Software_support
[5 See also]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#See_also
[6 References]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#References
[7 External links]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#External_links
[edit]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&action=edit&section=1
[300px-NUMA.svg.png]: /images/20220823/8d2915948e154c048d6977a3fc607022.png
[300px-NUMA.svg.png 1]: http://en.wikipedia.org/wiki/File:NUMA.svg
[magnify-clip.png]: http://bits.wikimedia.org/static-1.24wmf11/skins/common/images/magnify-clip.png
[cache memory]: http://en.wikipedia.org/wiki/Cache_memory
[cache misses]: http://en.wikipedia.org/wiki/Cache_miss
[2]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-2
[servers]: http://en.wikipedia.org/wiki/Server_%28computing%29
[3]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-acm-zmajo-3
[multi-channel memory architecture]: http://en.wikipedia.org/wiki/Multi-channel_memory_architecture
[4]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-4
[Nehalem]: http://en.wikipedia.org/wiki/Nehalem_%28microarchitecture%29
[Tukwila]: http://en.wikipedia.org/wiki/Tukwila_%28processor%29
[5]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-5
[chipset]: http://en.wikipedia.org/wiki/Chipset
[Quick Path Interconnect]: http://en.wikipedia.org/wiki/Intel_QuickPath_Interconnect
[6]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-6
[Opteron]: http://en.wikipedia.org/wiki/Opteron
[HyperTransport]: http://en.wikipedia.org/wiki/HyperTransport
[edit 1]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&action=edit&section=2
[300px-Hwloc.png]: /images/20220823/aaf6ab2fbc2c4456abacb978888d1400.png
[300px-Hwloc.png 1]: http://en.wikipedia.org/wiki/File:Hwloc.png
[Bulldozer]: http://en.wikipedia.org/wiki/Bulldozer_%28microarchitecture%29
[cache]: http://en.wikipedia.org/wiki/CPU_cache
[locality of reference]: http://en.wikipedia.org/wiki/Locality_of_reference
[cache coherence]: http://en.wikipedia.org/wiki/Cache_coherence
[von Neumann architecture]: http://en.wikipedia.org/wiki/Von_Neumann_architecture
[7]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-7
[8]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-8
[MESIF protocol]: http://en.wikipedia.org/wiki/MESIF_protocol
[Scalable Coherent Interface]: http://en.wikipedia.org/wiki/Scalable_Coherent_Interface
[IEEE]: http://en.wikipedia.org/wiki/IEEE
[9]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-9
[10]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-10
[AMD Opteron]: http://en.wikipedia.org/wiki/AMD_Opteron
[Intel]: http://en.wikipedia.org/wiki/Intel_Corporation
[Itanium]: http://en.wikipedia.org/wiki/Itanium
[HP 1]: http://en.wikipedia.org/wiki/Hewlett_Packard
[MIPS]: http://en.wikipedia.org/wiki/MIPS_architecture
[Alpha 21364]: http://en.wikipedia.org/wiki/Alpha_21364
[edit 2]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&action=edit&section=3
[cluster computing]: http://en.wikipedia.org/wiki/Cluster_computing
[virtual memory]: http://en.wikipedia.org/wiki/Virtual_memory
[edit 3]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&action=edit&section=4
[Microsoft]: http://en.wikipedia.org/wiki/Microsoft
[Windows 7]: http://en.wikipedia.org/wiki/Windows_7
[Windows Server 2008 R2]: http://en.wikipedia.org/wiki/Windows_Server_2008_R2
[11]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-11
[Java 7]: http://en.wikipedia.org/wiki/Java_7
[garbage collector]: http://en.wikipedia.org/wiki/Garbage_collector
[12]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-12
[Linux kernel]: http://en.wikipedia.org/wiki/Linux_kernel
[13]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-13
[14]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-14
[15]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-15
[huge pages]: http://en.wikipedia.org/wiki/Huge_page
[sysctl]: http://en.wikipedia.org/wiki/Sysctl
[16]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-16
[17]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-17
[18]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_note-18
[OpenSolaris]: http://en.wikipedia.org/wiki/OpenSolaris
[edit 4]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&action=edit&section=5
[Uniform memory access]: http://en.wikipedia.org/wiki/Uniform_memory_access
[Cache only memory architecture]: http://en.wikipedia.org/wiki/Cache_only_memory_architecture
[Scratchpad memory]: http://en.wikipedia.org/wiki/Scratchpad_memory
[Supercomputer]: http://en.wikipedia.org/wiki/Supercomputer
[HiperDispatch]: http://en.wikipedia.org/wiki/HiperDispatch
[edit 5]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&action=edit&section=6
[Jump up to_ _a]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-nyu-numa_1-0
[_b]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-nyu-numa_1-1
[_Non-Uniform Memory Access _NUMA]: http://cs.nyu.edu/~lerner/spring10/projects/NUMA.pdf
[Jump up]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-2
[_A Case for NUMA-aware Contention Management on Multicore Systems]: https://www.usenix.org/legacy/event/atc11/tech/final_files/Blagodurov.pdf
[Jump up to_ _a 1]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-acm-zmajo_3-0
[_b 1]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-acm-zmajo_3-1
[_Memory System Performance in a NUMA Multicore Multiprocessor]: http://people.inf.ethz.ch/zmajo/publications/11-systor.pdf
[Jump up 1]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-4
[Intel Dual-Channel DDR Memory Architecture White Paper]: http://web.archive.org/web/20110929024052/http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf
[KB]: http://en.wikipedia.org/wiki/Kilobyte
[the original]: http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf
[Jump up 2]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-5
[http_www.intel.com_pressroom_archive_reference_whitepaper_QuickPath.pdf]: http://www.intel.com/pressroom/archive/reference/whitepaper_QuickPath.pdf
[Jump up 3]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-6
[http_www.intel.com_pressroom_archive_releases_2007_20070918corp_b.htm]: http://www.intel.com/pressroom/archive/releases/2007/20070918corp_b.htm
[Jump up 4]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-7
[ccNUMA_ Cache Coherent Non-Uniform Memory Access]: http://www.slideshare.net/networksguy/ccnuma-cache-coherent-nonuniform-memory-access
[Jump up 5]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-8
[_Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures]: http://www.cs.berkeley.edu/~kubitron/cs258/handouts/papers/p80-stenstrom.pdf
[Jump up 6]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-9
[_The Scalable Coherent Interface and Related Standards Projects]: http://www.slac.stanford.edu/cgi-wrap/getdoc/slac-pub-5656.pdf
[Stanford Linear Accelerator Center]: http://en.wikipedia.org/wiki/Stanford_Linear_Accelerator_Center
[Jump up 7]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-10
[The NumaChip enables cache coherent low cost shared memory]: http://www.numascale.com/numa_technology.html
[Jump up 8]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-11
[NUMA Support _MSDN]: http://msdn.microsoft.com/en-us/library/windows/desktop/aa363804%28v=vs.85%29.aspx
[Jump up 9]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-12
[Java HotSpot_ Virtual Machine Performance Enhancements]: http://docs.oracle.com/javase/7/docs/technotes/guides/vm/performance-enhancements-7.html#numa
[Jump up 10]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-13
[Linux Scalability Effort_ NUMA Group Homepage]: http://lse.sourceforge.net/numa/
[Jump up 11]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-14
[1.8. Automatic NUMA balancing]: http://kernelnewbies.org/Linux_3.8#head-c16d4288b51f0b50fbf615657e81b0db643fa7a0
[Jump up 12]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-15
[_NUMA in a hurry]: https://lwn.net/Articles/524977/
[LWN.net]: http://en.wikipedia.org/wiki/LWN.net
[Jump up 13]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-16
[1.6. Improved performance in NUMA systems]: http://kernelnewbies.org/Linux_3.13#head-d29c7db2e73bc464eb67ed8de953d0bfc9841636
[Jump up 14]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-17
[Documentation_sysctl_kernel.txt]: https://www.kernel.org/doc/Documentation/sysctl/kernel.txt
[Jump up 15]: http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access#cite_ref-18
[_NUMA scheduling progress]: https://lwn.net/Articles/568870/
[Free On-line Dictionary of Computing]: http://en.wikipedia.org/wiki/Free_On-line_Dictionary_of_Computing
[GFDL]: http://en.wikipedia.org/wiki/GNU_Free_Documentation_License
[edit 6]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&action=edit&section=7
[NUMA FAQ]: http://lse.sourceforge.net/numa/faq/
[Page-based distributed shared memory]: http://cs.gmu.edu/cne/modules/dsm/yellow/page_dsm.html
[OpenSolaris NUMA Project]: http://www.opensolaris.org/os/community/performance/numa/
[Introduction video for the Alpha EV7 system architecture]: http://h18002.www1.hp.com/alphaserver/nextgen/overview.wmv
[More videos related to EV7 systems_ CPU_ IO_ etc]: http://www.alphaprocessors.com/
[NUMA optimization in Windows Applications]: http://developer.amd.com/pages/1162007106.aspx
[NUMA Support in Linux at SGI]: http://oss.sgi.com/projects/numa/
[Intel Tukwila]: http://www.realworldtech.com/page.cfm?NewsID=361&date=05-05-2006#361/
[Intel QPI _CSI_ explained]: http://www.realworldtech.com/page.cfm?ArticleID=RWT082807020032
[current Itanium NUMA systems]: http://www.sql-server-performance.com/articles/per/high_call_volume_NUMA_p1.aspx
[http_en.wikipedia.org_w_index.php_title_Non-uniform_memory_access_oldid_611303860]: http://en.wikipedia.org/w/index.php?title=Non-uniform_memory_access&oldid=611303860
[Categories]: http://en.wikipedia.org/wiki/Help:Category
[Parallel computing]: http://en.wikipedia.org/wiki/Category:Parallel_computing
[Computer memory]: http://en.wikipedia.org/wiki/Category:Computer_memory