MII xlinx ip 参考

浅浅的花香味﹌ 2022-12-11 02:27 89阅读 0赞

1、if.v

//------------------------------------------------------------------------------
    // File       : bd_71fb_mac_0_mii_if.v
    // Author     : Xilinx Inc.
    // -----------------------------------------------------------------------------
    // (c) Copyright 2009 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    // -----------------------------------------------------------------------------
    // Description:  This module creates a Media Independent
    //               Interface (MII) by instantiating Input/Output buffers
    //               and Input/Output flip-flops as required.
    //
    //               This interface is used to connect the Ethernet MAC to
    //               an external Ethernet PHY via MII connection.
    //
    //               The MII transmitter clocking logic is also defined here: the
    //               transmitter clock received from the PHY is unique and cannot be
    //               shared across multiple instantiations of the core.
    //
    //               The MII receiver clocking logic is also defined here: the
    //               receiver clock received from the PHY is unique and cannot be
    //               shared across multiple instantiations of the core.:
    //
    //------------------------------------------------------------------------------
    
    `timescale 1 ps / 1 ps
    
    
    module bd_71fb_mac_0_mii_if (
        // Synchronous resets
        input            tx_reset,
        input            rx_reset,
    
        // The following ports are the MII physical interface: these will be at
        // pins on the FPGA
        output     [3:0] mii_txd,
        output           mii_tx_en,
        output           mii_tx_er,
        input            mii_tx_clk,
        input      [3:0] mii_rxd,
        input            mii_rx_dv,
        input            mii_rx_er,
        input            mii_rx_clk,
    
        // The following ports are the internal connections from IOB logic to
        // the TEMAC core
        input      [3:0] txd_from_mac,
        input            tx_en_from_mac,
        input            tx_er_from_mac,
        output reg [3:0] rxd_to_mac   = 0,
        output reg       rx_dv_to_mac = 0,
        output reg       rx_er_to_mac = 0,
    
        // Receiver clock for the MAC and Client Logic
        output           rx_clk,
    
        // Transmitter clock for the MAC and Client Logic
        output           tx_clk
        );
    
    
      //----------------------------------------------------------------------------
      // internal signals
      //----------------------------------------------------------------------------
    
      wire            mii_tx_clk_ibuf;
      reg    [3:0]    mii_txd_obuf;
      reg             mii_tx_en_obuf;
      reg             mii_tx_er_obuf;
      wire   [3:0]    mii_rxd_ibuf;
      wire            mii_rx_dv_ibuf;
      wire            mii_rx_er_ibuf;
      wire            mii_rx_clk_ibuf;
    
      wire            tx_clk_int;
      wire            rx_clk_int;
    
      //----------------------------------------------------------------------------
      // Input/Output Buffers
      //----------------------------------------------------------------------------
    
      //----------------------------------------------------------------------------
      // MII
      //----------------------------------------------------------------------------
    
      IBUF mii_tx_clk_ibuf_i (
         .I              (mii_tx_clk),
         .O              (mii_tx_clk_ibuf)
      );
      
      OBUF mii_tx_en_obuf_i (
         .I              (mii_tx_en_obuf),
         .O              (mii_tx_en)
      );
      
      OBUF mii_tx_er_obuf_i (
         .I              (mii_tx_er_obuf),
         .O              (mii_tx_er)
      );
      
      genvar loopa;
      generate for (loopa=0; loopa<4; loopa=loopa+1)
        begin : obuf_data
          OBUF mii_txd_obuf_i (
             .I              (mii_txd_obuf[loopa]),
             .O              (mii_txd[loopa])
          );
        end
      endgenerate  
      
      IBUF mii_rx_clk_ibuf_i (
         .I              (mii_rx_clk),
         .O              (mii_rx_clk_ibuf)
      );
      
      IBUF mii_rx_dv_ibuf_i (
         .I              (mii_rx_dv),
         .O              (mii_rx_dv_ibuf)
      );
      
      IBUF mii_rx_er_ibuf_i (
         .I              (mii_rx_er),
         .O              (mii_rx_er_ibuf)
      );
      
      genvar loopi;
      generate for (loopi=0; loopi<4; loopi=loopi+1)
        begin : ibuf_data
          IBUF mii_rxd_ibuf_i (
             .I              (mii_rxd[loopi]),
             .O              (mii_rxd_ibuf[loopi])
          );
        end
      endgenerate 
       
      
      //----------------------------------------------------------------------------
      // MII Transmitter Clock Management :
      //----------------------------------------------------------------------------
    
    
      // The MAC transmitter clock at 10/100 speeds is provided by the PHY
    
      // Route MII Tx clock onto a regional clock network.
       BUFR bufr_mii_tx_clk (
          .I                (mii_tx_clk_ibuf),
          .CE               (1'b1),
          .CLR              (1'b0),
          .O                (tx_clk_int)
       );
    
      
      // Route the internal clock to the output port
      assign tx_clk = tx_clk_int;
    
    
       //---------------------------------------------------------------------------
       // MII Transmitter Logic :
       // drive TX signals through IOBs onto MII interface
       //---------------------------------------------------------------------------
    
       // Infer IOB Output flip-flops.
       always @(posedge tx_clk_int)
       begin
          mii_tx_en_obuf <= tx_en_from_mac;
          mii_tx_er_obuf <= tx_er_from_mac;
          mii_txd_obuf   <= txd_from_mac;
       end
    
    
       //---------------------------------------------------------------------------
       // MII Receiver Clock Logic
       //---------------------------------------------------------------------------
    
      // The MAC receiver clock at 10/100 speeds is provided by the PHY
    
      // Route MII Rx clock onto a regional clock network.
       BUFR bufr_mii_rx_clk (
          .I                (mii_rx_clk_ibuf),
          .CE               (1'b1),
          .CLR              (1'b0),
          .O                (rx_clk_int)
       );
    
    
      // Route the internal clock to the output port
      assign rx_clk = rx_clk_int;
    
    
      //----------------------------------------------------------------------------
      // MII Receiver Logic : receive RX signals through IOBs from MII interface
      //----------------------------------------------------------------------------
    
       // Infer IOB Input flip-flops.
       always @(posedge rx_clk_int)
       begin
          rx_dv_to_mac <= mii_rx_dv_ibuf;
          rx_er_to_mac <= mii_rx_er_ibuf;
          rxd_to_mac   <= mii_rxd_ibuf;
       end
    
    
    
    endmodule

2、xdc

# PART is virtex7 xc7v2000tflg1925
    
    ############################################################
    # Clock Period Constraints                                 #
    ############################################################
    
    ############################################################
    # RX Clock period Constraints (per instance)               #
    ############################################################
    # Receiver clock period constraints: please do not relax
    create_clock -period 40 [get_ports mii_rx_clk]
    
    ############################################################
    # MII TX Clock period Constraints (per instance)               #
    ############################################################
    create_clock -period 40 [get_ports mii_tx_clk]
    
    ############################################################
    # External MII Constraints                                #
    ############################################################
    
    ############################################################
    # Physical Interface Constraints
    ############################################################
    # MII Transmitter/Receiver Constraints:  place flip-flops in IOB
    set_property IOB TRUE [get_cells {mii_interface/mii_txd*reg[*]}]
    set_property IOB TRUE [get_cells {mii_interface/mii_tx_e*reg}]
    set_property IOB TRUE [get_cells {mii_interface/rx*_to_mac*reg}]
    set_property IOB TRUE [get_cells {mii_interface/rx*_to_mac*reg[*]}]
    
    
    #
    ####
    #######
    ##########
    #############
    #################
    #BLOCK CONSTRAINTS
    
    
    
    #
    ####
    #######
    ##########
    #############
    #################
    #CORE CONSTRAINTS
    
    
    
    ############################################################
    # Crossing of Clock Domain Constraints: please do not edit #
    ############################################################
    
    # control signal is synced separately so we want a max delay to ensure the signal has settled by the time the control signal has passed through the synch
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/flow/rx_pause/pause*to_tx_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/flow/tx_pause/count_set*reg}] 32 -datapath_only
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/flow/rx_pause/pause*to_tx_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/flow/tx_pause/pause_count*reg[*]}] 32 -datapath_only
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/flow/rx_pause/pause_req_to_tx_int_reg}] -to [get_cells {bd_71fb_mac_0_core/flow/tx_pause/sync_good_rx/data_sync_reg0}] 6 -datapath_only
    
    # false path due to synced control path
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/*statistics_counters/rd_data_ref_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/*statistics_counters/ip2bus_data_reg[*]}] 6 -datapath_only
    # CDC from the Tx and Rx statistics to the statistic counter logic
    set_max_delay -from [get_cells {vector_decode_inst/inc_vector_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/*statistics_counters/general_statisic_control[*].general_statisics/sync_inc_vector/data_sync_reg0}] 6 -datapath_only
    set_max_delay -from [get_cells {vector_decode_inst/inc_vector_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/*statistics_counters/frame_size_bin_control1[*].frame_size_stats1/sync_inc_vector/data_sync_reg0}] 6 -datapath_only
    set_max_delay -from [get_cells {vector_decode_inst/inc_vector_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/*statistics_counters/frame_size_bin_control2[*].frame_size_stats2/sync_inc_vector/data_sync_reg0}] 6 -datapath_only
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/*statistics_counters/*/accumulator_gray_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/*statistics_counters/*/accum_gray_resync[*].sync_accum_gray_i/data_sync_reg0}] 6 -datapath_only
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/*statistics_counters/response_toggle_reg}] -to [get_cells {bd_71fb_mac_0_core/*statistics_counters/sync_response/data_sync_reg0}] 6 -datapath_only
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/*statistics_counters/request_toggle_reg}] -to [get_cells {bd_71fb_mac_0_core/*statistics_counters/sync_request/data_sync_reg0}] 6 -datapath_only
    
    
    ############################################################
    # Ignore paths to resync flops
    ############################################################
    set_false_path -to [get_pins -filter {REF_PIN_NAME =~ PRE} -of [get_cells -hier -regexp {.*\/async_rst.*}]]
    set_false_path -to [get_pins -filter {REF_PIN_NAME =~ CLR} -of [get_cells -hier -regexp {.*\/async_rst.*}]]
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/addr_filter_top/addr_regs.promiscuous_mode_reg_reg}] -to [get_cells {bd_71fb_mac_0_core/addr_filter_top/address_filter_inst/resync_promiscuous_mode/data_sync_reg0}] 6 -datapath_only
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/addr_filter_top/addr_regs.filter_enable_reg_reg[*]}] -to [get_cells {bd_71fb_mac_0_core/addr_filter_top/address_filter_inst/address_filters[*].sync_enable/data_sync_reg0}] 6 -datapath_only
    set_max_delay -from [get_cells {bd_71fb_mac_0_core/*managen/conf/update_pause_ad_int_reg}] -to [get_cells {bd_71fb_mac_0_core/addr_filter_top/address_filter_inst/sync_update/data_sync_reg0}] 6 -datapath_only
    
    # set a false path for the clock path from the address filter dist rams
    # the paths we care about timing are either the write interface OR the read interface
    # this path is from the write to the read which should be ignored
    set_false_path -from [get_cells -hierarchical -filter {NAME =~ *bd_71fb_mac_0_core/addr_filter_top/address_filter_inst/*/DP}] -to  [get_cells -hierarchical -filter {NAME =~ *bd_71fb_mac_0_core/addr_filter_top/address_filter_inst/*addr*/bit_match*reg[*]}]
    
    # the mdio interface is clocked from the axi clock but the clock is so slow is can be considered to be data
    # the data related outputs are output on the falling edge of the MDC output so both can simply be considered to be multicycle paths
    set_multicycle_path 10 -setup -from [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.miim_clk_int_reg}  ] -throu [get_ports mdc]
    set_multicycle_path 9 -hold -from   [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.miim_clk_int_reg}  ] -throu [get_ports mdc]
    set_multicycle_path 10 -setup -from [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.phy/enable_reg_reg}] -throu [get_ports mdc]
    set_multicycle_path 9 -hold -from   [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.phy/enable_reg_reg}] -throu [get_ports mdc]
    set_multicycle_path 10 -setup -from [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.phy/mdio*reg}      ] -throu [get_ports mdio_o ] 
    set_multicycle_path 9 -hold -from   [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.phy/mdio*reg}      ] -throu [get_ports mdio_o ] 
    set_multicycle_path 10 -setup -from [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.phy/mdio*reg}      ] -throu [get_ports mdio_t ] 
    set_multicycle_path 9 -hold -from   [get_cells {bd_71fb_mac_0_core/*managen/mdio_enabled.phy/mdio*reg}      ] -throu [get_ports mdio_t ] 
    # mdio has timing implications but slow interface so relaxed
    set_false_path  -to [get_cells -hier -filter {NAME =~ *managen/mdio_enabled.phy/mdio_in_reg1_reg}]

\--------------------

############################################################
    # RX Clock period Constraints (per instance)               #
    ############################################################
    # Receiver clock period constraints: please do not relax
    set rx_clk [get_clocks -of [get_ports mii_rx_clk]]
    
    ############################################################
    # Obtain input clocks from top level XDC                         #
    ############################################################
    set ip_gtx_clk     [get_clocks -of_objects [get_ports gtx_clk]]
    
    set ip_mii_tx_clk  [get_clocks -of_objects [get_ports mii_tx_clk]]
    
    #
    ####
    #######
    ##########
    #############
    #################
    #BLOCK CONSTRAINTS
    
    
    # Define data valid window with respect to the clock.
    # The spec states that, worst case, the data is valid 10 ns before the clock edge.
    # The worst case it to provide 10 ns hold time (a 20 ns window in total)
    set_input_delay -clock $rx_clk -max 30            [get_ports {mii_rxd[*] mii_rx_er mii_rx_dv}]
    set_input_delay -clock $rx_clk -min 10 -add_delay [get_ports {mii_rxd[*] mii_rx_er mii_rx_dv}]
    
    ############################################################
    # Crossing of Clock Domain Constraints: please do not edit #
    ############################################################
    
    # set a false path for the IPIF
    set_max_delay -from [get_cells {axi4_lite_ipif/axi4_lite_ipif_top_wrapper/axi_lite_top/*/bus2ip_addr_i_reg[*]}] -to $ip_gtx_clk 6 -datapath_only
    
    # set a false path for the static config registers
    set_false_path -from [get_cells {bd_71fb_mac_0_core/*managen/conf/int_*reg[*]}] -to $ip_gtx_clk
    set_false_path -from [get_cells {bd_71fb_mac_0_core/*managen/conf/int_*reg[*]}] -to $ip_mii_tx_clk
    set_false_path -from [get_cells {bd_71fb_mac_0_core/*managen/conf/int_*reg[*]}] -to $rx_clk
    set_false_path -from [get_cells {bd_71fb_mac_0_core/*managen/conf/int_*reg}] -to $ip_gtx_clk
    set_false_path -from [get_cells {bd_71fb_mac_0_core/*managen/conf/int_*reg}] -to $ip_mii_tx_clk
    set_false_path -from [get_cells {bd_71fb_mac_0_core/*managen/conf/int_*reg}] -to $rx_clk