高速缓存存储器的组织结构_计算机科学组织| 高速缓存存储器

红太狼 2023-03-05 11:55 8阅读 0赞

高速缓存存储器的组织结构

## 高速缓存存储器 **(**Cache Memory**)** ##

*  **Cache memory** is a fast memory which is smaller in size, it is used as the intermediate memory between the CPU and Main Memory which objective is to support CPU access with a minimum delay.
    
    **高速缓冲存储器**是一种较小的快速存储器，用作CPU和主存储器之间的中间存储器，目的是以最小的延迟支持CPU访问。
 *  CPU performs the read and write operation on a cache memory as the functioning of the cache memory is hidden from both user and system programs.
    
    由于对用户程序和系统程序都隐藏了高速缓存的功能，因此CPU会对高速缓存进行读取和写入操作。
 *  A system with a **cache memory** delivers high performance and offers high throughput.
    
    具有**高速缓存**的系统可提供高性能并提供高吞吐量。
 *  Generally, cache consists of cache data memory and tag. Memory words are stored in a cache data memory and then these words are grouped into a block. Basic data transfer unit between main memory and cache is a block of words.
    
    通常，缓存由缓存数据存储器和标签组成。 存储字存储在高速缓存数据存储器中，然后将这些字分组为一个块。 主存储器和高速缓存之间的基本数据传输单元是一个字块。

Each cache block is then marked up with the block address which is referred as a tag. In this case, tag indicates the part of the memory space from which the block belongs.

然后，每个高速缓存块都用称为标签的块地址标记。 在这种情况下，标记指示该块所属的存储空间部分。

![Cache Memory Structure][]

Each cache block is then marked up with the block address which is referred as a tag. In this case, the tag indicates the part of the memory space from which the block belongs.

然后，每个高速缓存块都用称为标签的块地址标记。 在这种情况下，标签指示该块所属的存储空间部分。

### 缓存一致性 **(**Cache Coherence**)** ###

As it’s known, the cache has improved the performance of a system. However, there is a creation of a problem known as a coherence problem. In a single CPU system, two copies of the same data, one in the cache memory and another one in main memory may become different. Therefore by this content of cache and main memory can be altered by more than one device, by which it can result in inconsistencies in the value of cache and main memory.

众所周知，缓存提高了系统的性能。 但是，产生了称为相干问题的问题。 在单个CPU系统中，同一数据的两个副本(一个在高速缓存中，另一个在主存储器中)可能变得不同。 因此，可以通过一个以上的设备来更改缓存和主存储器的内容，从而导致缓存和主存储器的值不一致。

**Techniques for cache coherence**

**缓存一致性技术**

1.  **Write through:** In this technique write the data in the cache and in main memory, which will always keep the two copies of data consistent.
    
    **直写：**通过此技术，可将数据写入高速缓存和主存储器中，这将始终保持数据的两个副本一致。
2.  **Write block:** In this method, updates are made in the cache, by setting a bit called update bit. Only those blocks whose updates bit is set is replaced in the main memory.
    
    **写块：**在这种方法中，通过设置称为更新位的位在缓存中进行更新。 主存储器中仅替换已设置更新位的块。
3.  **Instruction cache:** This is a technique, which is employed for accessing only the instruction and nothing else. As we know, the instruction does not change, as there will not be any inconsistency.
    
    **指令缓存：**这是一种技术，仅用于访问指令，而不能访问其他任何内容。 我们知道，指令不会改变，因为不会有任何不一致。

**Cache coherence strategies**

**缓存一致性策略**

Cache strategies have been divided into two categories:

缓存策略分为两类：

1.  **Software solution:** In software solution the problem of cache coherence is managed entirely by the compiler and operating system. By this, there is no need of circuitry for managing the cache coherence scheme.
    
    **软件解决方案：**在软件解决方案中，缓存一致性问题完全由编译器和操作系统管理。 由此，不需要用于管理高速缓存一致性方案的电路。
2.  **Hardware solution:** These are referred to as cache coherence protocols. By this protocol, inconsistency can be handled during runtime, which leads to a more effective utilization of a cache and improved performance.
    
    **硬件解决方案：**这些被称为缓存一致性协议。 通过此协议，可以在运行时处理不一致问题，从而可以更有效地利用缓存并提高性能。

**Replacement algorithm of cache memory**

**缓存的替换算法**

When the cache is full, there is a need for replacement algorithm for replacing the cache block with a new block. For achieving the high-speed such types of the algorithm is implemented in hardware. In the cache memory, there are three types of replacement algorithm are used that are:

当高速缓存已满时，需要替换算法以将高速缓存块替换为新块。 为了实现高速，这种类型的算法在硬件中实现。 在高速缓存存储器中，使用了三种类型的替换算法：

1.  Random replacement policy.
    
    随机更换政策。
2.  First in first Out (FIFO) replacement policy
    
    先进先出(FIFO)替换策略
3.  Least recently used (LCU) replacement policy.
    
    最近最少使用(LCU)替换策略。

**1) Random replacement policy**

**1)随机更换政策**

This is a very simple algorithm which used to choose the block to be overwritten at random. In this algorithm replace any cache line by using random selection. It is an algorithm which is simple and has been found to be very effective in practice.

这是一种非常简单的算法，用于随机选择要覆盖的块。 在此算法中，通过使用随机选择来替换任何高速缓存行。 这是一种简单的算法，已在实践中被发现非常有效。

**2) First in first out (FIFO)**

**2)先进先出(FIFO)**

In this algorithm replace the cache block which is having the longest time stamp. While using this technique there is no need of updating when a hit occurs but when there is a miss occur then the block is put into an empty block and the counter values are incremented by one.

在此算法中，替换具有最长时间戳的缓存块。 使用此技术时，不需要在发生命中时进行更新，但是当发生未命中时，则将该块放入一个空块中，并将计数器值加1。

**3) Least recently used (LRU)**

**3)最近最少使用(LRU)**

In the LRU, replace the cache block which is having the less reference with the longest time stamp. In this case also when a hit occurs when the counter value will be set to 0 but when the miss occurs there will be arising of two possibilities in which one possibility is that counter value is set as 0 and in another possibility, the counter value can be incremented as 1.

在LRU中，用最长的时间戳替换引用较少的缓存块。 在这种情况下，当计数器值将被设置为0但发生未命中时，也会发生两种情况，其中一种可能性是将计数器值设置为0，而另一种可能性是，计数器值可以递增为1。

> 翻译自: [https://www.includehelp.com/cso/cache-memory.aspx][https_www.includehelp.com_cso_cache-memory.aspx]

高速缓存存储器的组织结构

[Cache Memory Structure]: /images/20230208/92ce0d0c1ecf4d2eaa842ed5cae1b1f1.png
[https_www.includehelp.com_cso_cache-memory.aspx]: https://www.includehelp.com/cso/cache-memory.aspx