Quartus使用笔记

红太狼 2023-07-02 05:26 113阅读 0赞

## Quartus ##

### 使能DEV\_CLRn等特殊引脚功能 ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70][]

### 在bdf文件中检索网络net ###

选中网络,Ctrl+F,可以查找所需的net!

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 1][]

### LogicLock操作步骤 ###

**参考**：

![20200126221014734.png][]  ![20200126221005933.png][]

create new region

创建区域

1.  打开逻辑锁区域Logic Regions窗口 \[Alt+L\]

![20200126221101876.png][]

2、添加逻辑区域

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 2][]

3、定位逻辑锁在Chip Planner的区域：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 3][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 4][]

4、将设计模块**适配**到新建的Region

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 5][]

5、关闭Optimize I/O　选项

![20200126221342501.png][]

![20200126221343329.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 6][]

6、编译设计![2020012622140745.png][]

7、反标注节点位置\[未找到\]

![20200126221427129.png][]  
Altera建议使用增量式编译方式而不是使用逻辑锁，来保持当前的综合和适配结果！

### Incremental Compilation操作步骤 ###

**参考**：![20200126221457790.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 7][]

### ModelSim路径 ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 8][]

### 关闭网络连接 ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 9][]

### 生成TestBench模版 ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 10][]

执行结果：

![20200126221706784.png][]

<table style="margin-left:5.4pt;"> 
 <tbody> 
 <tr> 
 <td style="vertical-align:top;width:382.75pt;"> TestBench样例： </td> 
 </tr> 
 <tr> 
 <td style="vertical-align:top;width:382.75pt;"> //This is a simple modelSim simulation flow demo //Function: simple testbench of pll_tb.v //2004-12-2 Westor &nbsp; `timescale 1ns/100ps &nbsp; module pll_ram_tb (); &nbsp; reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; clk_in;&nbsp;&nbsp;&nbsp; //50MHz reg&nbsp;&nbsp; rst;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; //asynchronous reset, low-effect reg&nbsp; [7:0] data_in;&nbsp;&nbsp; //data to ram reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; wr_en;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; //wirte enable reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rd_en;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; //read enable reg&nbsp; [4:0] rd_addr;&nbsp;&nbsp;&nbsp;&nbsp; //read addrress &nbsp; wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; clk_out;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; //clock output, 100MHz wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; lock;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; //pll lock indicator wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; package_full; //indicate the ram is full&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; wire [7:0] data_out;&nbsp;&nbsp;&nbsp; //data to ram &nbsp; initial &nbsp;&nbsp;&nbsp;&nbsp; begin &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; clk_in = 0; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rst&nbsp;&nbsp;&nbsp; = 0; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; data_in = 8'h55; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rd_en&nbsp;&nbsp; = 1'bz; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; wr_en&nbsp;&nbsp; = 1'bz; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rd_addr = 5'b0; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # 500 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rst&nbsp;&nbsp;&nbsp;&nbsp; =1; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # 1500 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rst&nbsp;&nbsp;&nbsp;&nbsp; =0; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # 1700 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rst&nbsp;&nbsp;&nbsp;&nbsp; =1; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; repeat (9) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; write_ram; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; repeat (5) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; read_ram; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; repeat (8) &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; begin&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # 100 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; write_ram; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # 5 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; read_ram; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; end &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # 8000 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; $stop; &nbsp;&nbsp;&nbsp;&nbsp; end &nbsp; always # 10 clk_in =~clk_in; &nbsp; task write_ram; &nbsp;&nbsp;&nbsp;&nbsp; begin &nbsp;&nbsp;&nbsp;&nbsp; # 5 &nbsp;&nbsp;&nbsp;&nbsp; wr_en = 1; &nbsp;&nbsp;&nbsp;&nbsp; data_in = data_in + 1; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; # 20 &nbsp;&nbsp;&nbsp;&nbsp; wr_en = 1'bz; &nbsp;&nbsp;&nbsp;&nbsp; end&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; endtask &nbsp; &nbsp; task read_ram; &nbsp;&nbsp;&nbsp;&nbsp; begin &nbsp;&nbsp;&nbsp;&nbsp; # 5 &nbsp;&nbsp;&nbsp;&nbsp; rd_en = 1; &nbsp;&nbsp;&nbsp;&nbsp; rd_addr = rd_addr + 1; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; # 20 &nbsp;&nbsp;&nbsp;&nbsp; rd_en = 1'bz; &nbsp;&nbsp;&nbsp;&nbsp; end endtask &nbsp; &nbsp; pll_ram pll_ram_u1(clk_in, rst, &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; data_in, &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; wr_en, rd_en, rd_addr,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; clk_out, lock, &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; package_full, &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; data_out &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ); &nbsp; endmodule </td> 
 </tr> 
 </tbody> 
</table>

### **将测试文件添加到工程设置：** ###

重要-注意名称填写来自上一步骤生成的vt文件。

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 11][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 12][]

![20200126221831364.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 13][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 14][]

### 波形VWF文件仿真 ###

![2020012622200844.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 15][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 16][]![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 17][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 18][]![20200126222009914.png][]![20200126222009657.png][]

### Virtual Pin设置 ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 19][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 20][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 21][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 22][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 23][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 24][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 25][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 26][]

### Quartus II Support for Verilog 2001 ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 27][]

### 编译结果查看： ###

需要选中fitter中的summary，才能看到最终的结果：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 28][]

### 查看内部寄存器在ModelSim仿真的值： ###

f1.Maintain Hierachy 设置为 “on”

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 29][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 30][]

f2.使用层次化调用的方法即”.”，添加wire信号到要观测的寄存器

样例：wire name = 模块名.子实例名…端口定义名或寄存器名(一定不能用实例化的实参名)

![20200126225114511.png][]

![20200126225114515.png][]

![20200126225105711.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 31][]

**特殊情况**：SISR0寄存器虽然定义为reg\[15:0\]但由于某些位没有驱动，实际生成的网表是按SISR0\_0、SISR0\_1…来定义的，可以右击->view declaration在.vo文件查看。

![20200126225151171.png][]![20200126225142365.png][]![20200126225144121.png][]

![20200126225151191.png][]

![20200126225151226.png][]![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 32][]

PLL模块的输入时钟一定要和设置的实际输入时钟一致否则没有输出信号：

![20200126225227699.png][]

根据\`timescale 1ns/10ps定义来计算时钟输入inclk0。

(1ns是时间单位，10ps是仿真精度)

![20200126225248364.png][]

![20200126225239562.png][]

充分使用模版功能查看verilog运算符功能，以及systemverilog语法：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 33][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 34][]

### 使用verilog2001构建可定制参数的v文件： ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 35][]

1.使用了generate语法，但是还不属于systemverilog，**systemverilog****是verilog****的扩展，语法更简洁更灵活。**使用systemverilog可以更改文件后缀名为.sv或者在verilog HDL input选项选择SystemVerilog。

![20200126225346767.png][]

2.一开始编译不成功是因为使用了\`include语句，直接通过Add Files添加到工程即可。否则报错**：****…not support synthesizing nested module declaration!**这个问题困惑了很久，一只以为设置宏parameter参数的格式不对。

3.Genenrate语法一共3种：

Generate语法要求必须有begin,且begin后面必须有name(实例化使用)；genvar变量在一个文件中通用不能重复定义，变量名称不能一样，begin后面的name名称也是一样。

1)If:

2)Case:

2)For:

4、verilog2001的在quartus2的支持：***借助自带的******help******文档，这个功能是需要单独安装的在13.0sp1******版本quartus.***

![20200126225442535.png][]![20200126225451326.png][]

Quartus/13.0sp1/quartus/common/help/webhelp/master.htm\#mergedProjects/quartus/gl\_quartus\_welcome.htm

5、systemverilog 在 quartus2的支持：

同4.

//-----------------------------------------------------------------------------
 wire FANA_flag;
 wire FANB_flag;
 //`include "fan_det.v"//Wrong:can not add this words,case to false:Not support synthesizing nested module declaration.
 fan_det #(2) fan_det_inst
 (
 .clk(clk),//40mHz
 			.rst(rst2_n),
 .in({FANB_STUS,FANA_STUS}),//fan pin
 			.out({FANB_flag,FANA_flag}) //state out 
 );
 //---------------------------------------------------------------------------------------------
 /*
 Detect the fan state.
 */
 module fan_det
 #(parameter N=1)//the number of the fan.
 (
 input clk,//40mHz
 		input rst,
 input [N-1:0] in,//fan pin
 		output reg [N-1:0] out //state out 
 );
 reg clk_div; //0x1A286分频输出
 reg [15:0] clk_count; //分频计数器
 reg [15:0] min; //一分钟寄存器
 //
 reg [N-1:0] FAN_D1; //用于FAN_STUS输入同步，且转为单CLK脉冲
 reg [N-1:0] FAN_D2; 
 wire [N-1:0] FAN_trigger; //风扇单CLK脉冲输入
 //
 reg [15:0] FAN_count[0:N-1]; //风扇转速脉冲计数器 
 //
 assign FAN_trigger = (FAN_D1) & (~FAN_D2);//bit &
 always@(posedge clk or negedge rst) //同步
 begin
 if(~rst)
 begin
 FAN_D1 <= {N{1'b0}};
 FAN_D2 <= {N{1'b0}};
 end
 else
 begin
 FAN_D1 <= in;
 FAN_D2 <= FAN_D1;
 end
 end 
 //SystemVerilog
 /*
 ACTION: 	Set the Verilog Input Version for the file to SystemVerilog_2005 
 or save the file as a SystemVerilog Design File (.sv).
 */
 genvar i;
 genvar j;
 generate
 for(i=0;i<=N;i=i+1)
 begin:fan_cnt//name
 		always@(posedge clk or negedge rst)
 		 begin
 			 if(!rst)
 				FAN_count[i]<=16'h00;
 			 else
 				begin
 if(( min >= 16'h0BEB ) && ( FAN_trigger[i] ))//上电5秒后开始计数,FANA_STUS为高
 					 FAN_count[i] <= FAN_count[i] + 16'h01;
 				 if( min == 16'h5372 ) //计数35秒后，清零
 					 FAN_count[i] <= 16'h00;
 				end
 		 end
 end
 endgenerate
 //
 generate
 for(j=0;j<=N;j=j+1)
 begin:fan_cout//name
 		always@(posedge clk or negedge rst)
 		 begin
 			 if(!rst)
 				out[j] <= 1'b0;
 			 else
 				if( ( min >= 16'h5370 ) && ( min<=16'h5372 ) )
 				 begin
 			 if(FAN_count[j] >= 12'h3E8) //半分钟分扇发出的脉冲大于1000个
 						begin
 						 out[j] <= 1'b0;
 					 end
 					else
 						begin
 						 out[j] <= 1'b1; //小于风扇转速过低标志位置高
 						end
 					end
 		 end
 	end
 endgenerate
 endmodule

UDP使用：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 36][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 37][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 38][]

![20200126225601325.png][]

### 不可忽略的警告： ###

1、使用第三方EDA工具仿真PLL需要1ps的时间单位：

![20200126225719543.png][]

*  **Warning (202000): An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool.**

2、unsafe behavior 暗指毛刺glitch：

![20200126225746379.png][]

![20200126225757883.png][]

3、Modelsim Altera performance：

![2020012622583246.png][]

辅助编辑器Notepad++：quartus自带的编辑器功能有限，唯一特色就是具有Template功能

1、分栏功能使用：

左击文件的标签页不放拖到空白处，放开后选择“复制到另一视图”

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 39][]

右击分页线选择旋转可以改变分栏方向

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 40][]

2、更改文本的编码，在quartus中显示中文：

![20200126230034509.png][]

3、层次折叠及快捷键：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 41][]

折叠快捷键推荐”ALT+2”

![20200126230126598.png][]

4、快速打开文件所在的文件夹：

![20200126230151310.png][]

5、带颜色代码粘贴功能：

先选中要粘贴的代码，再选择”插件->NppExport->Copy RTF tp clipboard”

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 42][]

6、值得推荐的自带Template功能：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 43][]

芯片验证ＵＶＭ方法：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 44][]![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 45][]

仿真分类：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 46][]

Testbench参考模板：

![20200126230355552.png][]![20200126230408796.png][]

光标定位设置：

![20200126230424772.png][]

add wave语法：

![20200126230451545.png][]

![20200126230516788.png][]

<table style="width:341px;"> 
 <tbody> 
 <tr> 
 <td style="width:338px;"> add wave -hex -group CONTROL \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_15 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_14 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_13 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_12 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_11 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_10 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_9 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_8 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_7 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_6 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_5 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_4 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_3 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_2 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_1 \ /AILC_vlg_tst/i1/inst3/inst2/CONTROL_0 &nbsp; </td> 
 </tr> 
 </tbody> 
</table>

### force语句： ###

在两个仿真器中，force保持一个值直到它被release，而一个deposited值保持其值仅到信号更新。在Verilog-XL中， force命令使force节点减速，但可以在一个表达式和一个信号之间创建一个连续关系。它可以为一个位或部分赋值，而$deposit只能影响整个线网或寄存器。

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 47][]

### 使用相对NativeLink路径： ###

使用这种方式路径比较干净易于查看，没有特殊符号产生。

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 48][]

![20200126230623691.png][]

### 自定义仿真脚本 ###

先使用自动生成，拷贝修改后改为自定义，可以保留自己需要的波形及仿真操作：

![20200126230702736.png][]

同时关闭自动sim脚本生成功能，否则脚本回循环不能定位到上图指定的脚本：

![20200126230717370.png][]

关于路径空格报错：

有3种解决方式：

1、

![20200126230727758.png][]

2、在空格前加反斜杠

![20200126230814736.png][]

3、使用花括号

![20200126230827354.png][]

仿真文件：

VCD

![20200126230846927.png][]

![20200126230855808.png][]

Wlf文件

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 49][]

do文件

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 50][]

### Task & event: ###

![20200126230938119.png][]

### $monitor: ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 51][]

### Toggle Leaf Names: ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 52][]

### ModelSim保存波形设置: ###

![20200126224424367.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 53][]

![20200126224424425.png][]

### synthesis preserve: ###

这个命令不适用于端口，适用于内部逻辑，只要实际用到了该reg基本可以保留，

一般找不到（在modelsim的列表里查找）是因为虽然定义了实际没有使用到，被优化掉了。

![2020012622434271.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 54][]

### 引脚配置修改QSF文件: ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 55][]

### Quartus裁剪: ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 56][]

### Dsp builder 安装: ###

32位 dsp builder 安装步骤 2018.11.25 wuhou

先安装matlab，再重新安装dsp builder：

1、合并两个license文件，并新建LM\_LICENSE\_FILE路径在用户和系统环境变量

2、替换目录下的两个dll,原先的dll改为bk

C:\\altera\\13.0sp1\\quartus\\dsp\_builder\\bin

验证：找一个自带的demo,双击看是否可以编译及Export：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 57][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 58][]

Dsp builder  Path设置:

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 59][]

查看引脚配置类型:

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 60][]

### FIR IP核使用测试: ###

简介：

在时域中，FIR滤波器的输入/输出就是一个输入信号与单位脉冲相应的**卷积**。离散方程为y(n)=x(n)\*h(n)=∑x(k)h(n-k)=∑h(k)x(n-k)，其中y(n)为滤波输出，x(n)为采样数据，h(n)为滤波抽头系数.**设计FIR****滤波器就是要找到N****个系数**。**N-1****阶滤波器通常需要N****个系数描述，通常需要N****个乘法器和N-1****个2****输入加法器实现。**根据FIR表达式，滤波器实质上就是进行乘累加运算，乘累加的次数由滤波器阶数决定。其串行结构如图：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 61][]

对于滤波器的因数也可以用Matlab的FDATool工具得到，一般可在DSP程序中使用，对于FPGA可直接使用自带的IP 核。

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 62][]

![20200126224037762.png][]

实验参数：

36阶,16位无符号数据输入，带通(2.5K~7.5K)，采样频率设为20KHz，可以设置输入通道数，这里选择了1个作为测试，可视具体情况而定。

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 63][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 64][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 65][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 66][]

Matlab仿真文件说明：

一共四个文件，其中output.txt为执行之后的输出文件，主文件如下所示为fir\_1\_model.m直接运行即可看到滤波器效果。主要用来验证FIR滤波因数的正确性。

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 67][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 68][]

![20200126223805517.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 69][]

重要使用说明：

1、Quartus13.0在32位上可以使用FIR IP核，但64位电脑不行，对于64位电脑建议使用15.0版本。

2、同时对应的IP核需要对应的破解文件，否则仿真会报错，license见附录。

3、对于signal tap文件打开卡顿时由于你编译次数太多，保留了太多log,导致文件很大，建议删去。

![20200126223441405.png][]

4、想要读取ram模块内容时建议先打开![2020012622353112.png][]，把文件下载到FPGA，再打开![20200126223616201.png][]直接监控或者![20200126223649936.png][]读取状态并设置自己想要的标志位。Ram模块可以读取也可以通过Jtag写入注意选择正确的更新图标，不要弄反了^\_^。

5、大的工程尽量分开为几个小工程编译，否则时间太耗费了。

6、IP核的目录在 ![20200126223718617.png][]，和quartus是单独并列的一个文件夹，一共不到800MBits对于13.0，作为精简版如不需要可以去掉。**实际单独拷贝过来，试过不能用（会卡在启动界面上），还是需要完成安装。**

### EPCQ： ###

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 70][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 71][]

### 时序分析： ###

![20200126223251650.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 72][]

1、打开时序分析工具tools->TimeQuest Timing Analyzer

![20200126223129377.png][]

2、建立时序网表Netlist->Create Timing Netlist

![20200126223207635.png][]

3、新建sdc文件并编辑，插入Create Clock约束【告诉时序分析输入时钟的频率大小】，完全不需要手写任何代码

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 73][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 74][]

### 关于高版本打开低版本产生的错误警告可以通过修改qsf文件屏蔽 ###

![20200126223017489.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 75][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 76][]

singal tap:

改了出发条件的模式选项也需要重新编译：

![2020060618512850.png][]

[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70]: https://img-blog.csdnimg.cn/20200126220850376.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 1]: https://img-blog.csdnimg.cn/20200126220926144.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
[20200126221014734.png]: https://img-blog.csdnimg.cn/20200126221014734.png
[20200126221005933.png]: https://img-blog.csdnimg.cn/20200126221005933.png
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[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 2]: https://img-blog.csdnimg.cn/20200126221133946.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 3]: https://img-blog.csdnimg.cn/20200126221209258.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 4]: https://img-blog.csdnimg.cn/20200126221222864.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 5]: https://img-blog.csdnimg.cn/20200126221247649.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
[20200126221342501.png]: https://img-blog.csdnimg.cn/20200126221342501.png
[20200126221343329.png]: https://img-blog.csdnimg.cn/20200126221343329.png
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 6]: https://img-blog.csdnimg.cn/20200126221342266.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
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[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 9]: https://img-blog.csdnimg.cn/20200126221615988.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc=,size_16,color_FFFFFF,t_70
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