基于MIPS32的五级流水及中断控制器设计

末蓝、 2024-04-07 13:12 67阅读 0赞

设计题目：基于MIPS32的五级流水及中断控制器设计

目录  
一、设计实验条件 2  
二、设计任务及要求 2  
三、设计报告的内容 2  
其中，S2-S0 对应的功能表如下： 5  
根据原理图，我们可以得到 RS 触发器的真值表。 5  
二、实现一个 32 位的 ALU 9  
三、实现 RS 触发器 11  
其中我们预定义寄存器的值始终如下： 13  
2.测试的结果如下 14  
根据波形图，可以知道我们设计的 SUBU 指令的五级流水是正确的。二 、 32 位 ALU 测 试1.测试的核心代码如下 14  
h0 到 h7 分别是，加法，减法，或，与，带进位的加法和减法，A 取反，以及直接输出 A。比较结果，发现结果没有错误。根据波形图，可以知道我们设计的 15  
与真值表比较可以知道，当 SD 为 1 的时候，RD 为 0，Q 置 1；SD 为 0 的时 18  
endmodule 21  
endmodule 21  
endmodule 22  
./Code-ALU/add.v 24  
endmodule 25  
endmodule 25  
endmodule 25  
./Code-ALU/alu.v 26  
`include "define.v" 32 input wire[`SELECT\_WIDTH\] s, 32  
`ADD: begin 32 end 32 end 32 end 32 end 32`define InstValid 1’b0 //指令有效 40  
`define EXE_SUBU 6'b100011 40`define EXE\_SUBU\_OP 8’b00010001 40  
`define EXE_RES_ARITHMETIC 3'b100 40`define InstAddrBus 31:0 //ROM 的地址总线宽度 40  
./Code-SUB 指令/ex.v 41  
output reg\[`AluOpBus] aluop_o, output reg[`AluSelBus\] alusel\_o, output reg\[`RegBus] reg1_o, 44 reg[`RegBus\] imm; 44  
end else begin 44  
end 45  
end else begin 45  
end 45  
./Code-SUB 指令/id\_ex.v 46  
wire\[`RegAddrBus] id_wd_o; 51 wire[`RegBus\] ex\_reg2\_i; wire ex\_wreg\_i; wire\[`RegAddrBus] ex_wd_i; 51 wire ex_wreg_o; wire[`RegAddrBus\] ex\_wd\_o; wire\[`RegBus] ex_wdata_o; 51 wire mem_wreg_i; wire[`RegAddrBus\] mem\_wd\_i; wire\[`RegBus] mem_wdata_i; 51 wire mem_wreg_o; wire[`RegAddrBus\] mem\_wd\_o; wire\[`RegBus] mem_wdata_o; 51 wire wb_wreg_i; wire[`RegAddrBus\] wb\_wd\_i; wire\[`RegBus] wb_wdata_i; 51 wire reg2_read; wire[`RegBus\] reg1\_data; wire\[`RegBus] reg2_data; wire[`RegAddrBus\] reg1\_addr; wire\[`RegAddrBus] reg2_addr; 51 ./Code-SUB 指令/openmips_min_sopc_tb.v 55 input wire 58 input wire[`RegAddrBus\] raddr1, output reg\[`RegBus] rdata1, 58 input wire 58 input wire[`RegAddrBus\] raddr2, output reg\[`RegBus] rdata2 58 reg[`RegBus\] regs\[0:`RegNum-1]; 58 end 58`RegNumLog2’h0)) begin 58

一、设计实验条件  
计算机组成原理实验室

二、设计任务及要求  
设计并实现指令 SUBU rd. rs, rt；  
32 位 ALU；  
RS 触发器；  
三、设计报告的内容  
1.前言  
MIPS 架构 20 多年前由斯坦福大学开发，是一种简洁、优化、具有高度扩展性的 RISC 架构。它的基本特点是：包含大量的寄存器、指令数和字符、可视的管道延时时隙，这些特性使 MIPS 架构能够提供最高的每平方毫米性能和当今 SoC 设计中最低的能耗。  
我们知道，RISC 的一大特点是：大量使用寄存器。这是因为寄存器的存取可以在一个时钟周期内完成，同时使用寄存器也大大简化了寻址方式。与其相应 的，MIPS32 的指令中除加载（LDA）和存储（STO）指令外，都是使用寄存器或立即数作为操作数的。本文转载自http://www.biyezuopin.vip/onews.asp?id=15384，MIPS32 中的寄存器分为两类：通用寄存器（General Purpose Register, GPR）、特殊寄存器。  
MIPS32 架构定义了 32 个通用寄存器，使用 $0、$1…$31 表示，都是 32 位。其中 $0 般用做常量 0。

#! /usr/local/Cellar/icarus-verilog/10.3/bin/vvp
    :ivl_version "10.3 (stable)" "(v10_3)";
    :ivl_delay_selection "TYPICAL";
    :vpi_time_precision - 12;
    :vpi_module "system";
    :vpi_module "vhdl_sys";
    :vpi_module "v2005_math";
    :vpi_module "va_math";
    S_0x7fe43e5059a0 .scope module, "rs_tb" "rs_tb" 2 4;
     .timescale -9 -12;
    v0x7fe43e617030_0 .var "CLOCK_50", 0 0;
    v0x7fe43e6170c0_0 .var/i "high", 31 0;
    v0x7fe43e617150_0 .var/i "low", 31 0;
    v0x7fe43e6171e0_0 .net "q", 0 0, v0x7fe43e616050_0;  1 drivers
    v0x7fe43e617270_0 .net "qb", 0 0, v0x7fe43e615b90_0;  1 drivers
    v0x7fe43e617340_0 .var "r", 0 0;
    v0x7fe43e617410_0 .var "s", 0 0;
    E_0x7fe43e4009d0 .event posedge, v0x7fe43e616440_0;
    S_0x7fe43e400a50 .scope module, "rs0" "rs" 2 47, 3 3 0, S_0x7fe43e5059a0;
     .timescale -9 -12;
        .port_info 0 /INPUT 1 "clk"
        .port_info 1 /INPUT 1 "r"
        .port_info 2 /INPUT 1 "s"
        .port_info 3 /OUTPUT 1 "q"
        .port_info 4 /OUTPUT 1 "qb"
    v0x7fe43e616a90_0 .net "clk", 0 0, v0x7fe43e617030_0;  1 drivers
    v0x7fe43e616b60_0 .net "q", 0 0, v0x7fe43e616050_0;  alias, 1 drivers
    v0x7fe43e616c30_0 .net "qb", 0 0, v0x7fe43e615b90_0;  alias, 1 drivers
    v0x7fe43e616d00_0 .net "r", 0 0, v0x7fe43e617410_0;  1 drivers
    v0x7fe43e616d90_0 .net "rd", 0 0, v0x7fe43e6164e0_0;  1 drivers
    v0x7fe43e616ea0_0 .net "s", 0 0, v0x7fe43e617340_0;  1 drivers
    v0x7fe43e616f30_0 .net "sd", 0 0, v0x7fe43e6169a0_0;  1 drivers
    S_0x7fe43e400cb0 .scope module, "g1" "isnand" 3 15, 4 1 0, S_0x7fe43e400a50;
     .timescale -9 -12;
        .port_info 0 /INPUT 1 "a"
        .port_info 1 /INPUT 1 "b"
        .port_info 2 /OUTPUT 1 "c"
    v0x7fe43e400f00_0 .net "a", 0 0, v0x7fe43e6169a0_0;  alias, 1 drivers
    v0x7fe43e615ae0_0 .net "b", 0 0, v0x7fe43e616050_0;  alias, 1 drivers
    v0x7fe43e615b90_0 .var "c", 0 0;
    E_0x7fe43e400eb0 .event edge, v0x7fe43e400f00_0, v0x7fe43e615ae0_0;
    S_0x7fe43e615c60 .scope module, "g2" "isnand" 3 16, 4 1 0, S_0x7fe43e400a50;
     .timescale -9 -12;
        .port_info 0 /INPUT 1 "a"
        .port_info 1 /INPUT 1 "b"
        .port_info 2 /OUTPUT 1 "c"
    v0x7fe43e615ee0_0 .net "a", 0 0, v0x7fe43e6164e0_0;  alias, 1 drivers
    v0x7fe43e615f90_0 .net "b", 0 0, v0x7fe43e615b90_0;  alias, 1 drivers
    v0x7fe43e616050_0 .var "c", 0 0;
    E_0x7fe43e615e90 .event edge, v0x7fe43e615ee0_0, v0x7fe43e615b90_0;
    S_0x7fe43e616140 .scope module, "rd1" "isnand" 3 14, 4 1 0, S_0x7fe43e400a50;
     .timescale -9 -12;
        .port_info 0 /INPUT 1 "a"
        .port_info 1 /INPUT 1 "b"
        .port_info 2 /OUTPUT 1 "c"
    v0x7fe43e616390_0 .net "a", 0 0, v0x7fe43e617410_0;  alias, 1 drivers
    v0x7fe43e616440_0 .net "b", 0 0, v0x7fe43e617030_0;  alias, 1 drivers
    v0x7fe43e6164e0_0 .var "c", 0 0;
    E_0x7fe43e616360 .event edge, v0x7fe43e616390_0, v0x7fe43e616440_0;
    S_0x7fe43e6165e0 .scope module, "sd1" "isnand" 3 13, 4 1 0, S_0x7fe43e400a50;
     .timescale -9 -12;
        .port_info 0 /INPUT 1 "a"
        .port_info 1 /INPUT 1 "b"
        .port_info 2 /OUTPUT 1 "c"
    v0x7fe43e616830_0 .net "a", 0 0, v0x7fe43e617340_0;  alias, 1 drivers
    v0x7fe43e6168e0_0 .net "b", 0 0, v0x7fe43e617030_0;  alias, 1 drivers
    v0x7fe43e6169a0_0 .var "c", 0 0;
    E_0x7fe43e6167e0 .event edge, v0x7fe43e616830_0, v0x7fe43e616440_0;
        .scope S_0x7fe43e6165e0;
    T_0 ;
        %wait E_0x7fe43e6167e0;
        %load/vec4 v0x7fe43e616830_0;
        %load/vec4 v0x7fe43e6168e0_0;
        %or;
        %inv;
        %assign/vec4 v0x7fe43e6169a0_0, 0;
        %jmp T_0;
        .thread T_0, $push;
        .scope S_0x7fe43e616140;
    T_1 ;
        %wait E_0x7fe43e616360;
        %load/vec4 v0x7fe43e616390_0;
        %load/vec4 v0x7fe43e616440_0;
        %or;
        %inv;
        %assign/vec4 v0x7fe43e6164e0_0, 0;
        %jmp T_1;
        .thread T_1, $push;
        .scope S_0x7fe43e400cb0;
    T_2 ;
        %wait E_0x7fe43e400eb0;
        %load/vec4 v0x7fe43e400f00_0;
        %load/vec4 v0x7fe43e615ae0_0;
        %or;
        %inv;
        %assign/vec4 v0x7fe43e615b90_0, 0;
        %jmp T_2;
        .thread T_2, $push;
        .scope S_0x7fe43e615c60;
    T_3 ;
        %wait E_0x7fe43e615e90;
        %load/vec4 v0x7fe43e615ee0_0;
        %load/vec4 v0x7fe43e615f90_0;
        %or;
        %inv;
        %assign/vec4 v0x7fe43e616050_0, 0;
        %jmp T_3;
        .thread T_3, $push;
        .scope S_0x7fe43e5059a0;
    T_4 ;
        %pushi/vec4 1, 0, 32;
        %store/vec4 v0x7fe43e6170c0_0, 0, 32;
        %pushi/vec4 0, 0, 32;
        %store/vec4 v0x7fe43e617150_0, 0, 32;
        %end;
        .thread T_4;
        .scope S_0x7fe43e5059a0;
    T_5 ;
        %wait E_0x7fe43e4009d0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e6170c0_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617410_0, 0;
        %load/vec4 v0x7fe43e617150_0;
        %pad/s 1;
        %assign/vec4 v0x7fe43e617340_0, 0;
        %end;
        .thread T_5;
        .scope S_0x7fe43e5059a0;
    T_6 ;
        %vpi_call 2 36 "$dumpfile", "test.vcd" {
        0 0 0};
        %vpi_call 2 37 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x7fe43e5059a0 {
        0 0 0};
        %pushi/vec4 0, 0, 1;
        %store/vec4 v0x7fe43e617030_0, 0, 1;
    T_6.0 ;
        %delay 10000, 0;
        %load/vec4 v0x7fe43e617030_0;
        %inv;
        %store/vec4 v0x7fe43e617030_0, 0, 1;
        %jmp T_6.0;
        %end;
        .thread T_6;
        .scope S_0x7fe43e5059a0;
    T_7 ;
        %delay 130000, 0;
        %vpi_call 2 44 "$stop" {
        0 0 0};
        %end;
        .thread T_7;
    # The file index is used to find the file name in the following table.
    :file_names 5;
        "N/A";
        "<interactive>";
        "rs_tb.v";
        "./rs.v";
        "./nand.v";

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[528c286ab6af4cce8100a4e4dfcf5d23.png_pic_center]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/07/88dbbdb5b3004140876ded406aa51de8.png
[cac43635dc9c42358617b719b6d3dd4f.png_pic_center]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/07/9bb91f319fd44e8b96399a0d55108f34.png
[52838c8c85204c58bf5bedb98c360129.png_pic_center]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/07/b4bc1dea46bc49ad92664e886ce7f488.png
[31329239b5ce4fd9b46876b891a9d6c8.png_pic_center]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/07/3d77479671cb4585b2d093c41752bee5.png
[b18b6ecc11ed478a93e1c4c616095158.png_pic_center]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/07/fb7258424ca242739f93031fd9d6343e.png
[a50cc608aec4496188a13228ba28f81a.png_pic_center]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/07/c01f9b7cf9004be4a4fb68e89ef4e922.png