FPGA网表edf导出及仿真

墨蓝 2023-03-04 09:18 2阅读 0赞

[https://zhuanlan.zhihu.com/p/137433454][https_zhuanlan.zhihu.com_p_137433454]

Options中将-flatten\_hierarchy设为full，意思是模块综合后的层次结构全部为平级，只剩下顶层，这样产生的网表文件就不易被查看到层级关系了，可详见UG901的第11页

More Options选项设置为-mode out\_of\_context，原因是因为Vivado在综合的时候会自动将顶层的IO口自动插入buffer，而现在需要生成网表的模块往往不是顶层，生成的文件是需要被其他模块例化的，所以不能含有IO buffer，设为-mode out\_of\_context即表示不插入IO buffers，**注意mode前面有个"-"**，具体可详见UG901的第26页

//vivado 2017.4及以前
    write_verilog -mode port <design_name>.v
    
    //vivado 2018.1及以后
    write_verilog -mode synth_stub <design_name>.v
    
    //例如本次，文件名前面不加地址则默认保存在C:/Users/<user>/AppData/Roaming/Xilinx/Vivado/下
    write_verilog -mode synth_stub D:/fsm_test_top.v

//模块不包含Xilinx的IP
    write_edif <design_name>.edf
    
    //模块包含Xilinx的IP
    write_edif -security_mode all <design_name>.edf
    
    //本次模块中没有使用Xilinx的IP
    write_edif D:/fsm_test_top.edf

//--------------------------------------------------------------

[https://forums.xilinx.com/t5/Vivado/vivado%E7%94%9F%E6%88%90%E7%BD%91%E8%A1%A8-edf-%E6%96%87%E4%BB%B6-%E6%96%B0%E5%B7%A5%E7%A8%8B%E4%B8%AD%E4%B8%8D%E8%83%BD%E8%BF%9B%E8%A1%8C%E4%BB%BF%E7%9C%9F/m-p/1134183][https_forums.xilinx.com_t5_Vivado_vivado_E7_94_9F_E6_88_90_E7_BD_91_E8_A1_A8-edf-_E6_96_87_E4_BB_B6-_E6_96_B0_E5_B7_A5_E7_A8_8B_E4_B8_AD_E4_B8_8D_E8_83_BD_E8_BF_9B_E8_A1_8C_E4_BB_BF_E7_9C_9F_m-p_1134183]

## vivado生成网表（edf）文件，新工程中不能进行仿真 ##

Open synthesized design

write\_verilog -mode funcsim xxx.v

synth\_stub只是导出黑盒子模块声明。

edf本身是不能用于仿真的，必须借助write\_verilog导出仿真网表。关于不同仿真阶段的描述，可以参考UG900。

[https://www.xilinx.com/support/documentation/sw\_manuals/xilinx2020\_1/ug900-vivado-logic-simulation.pdf][https_www.xilinx.com_support_documentation_sw_manuals_xilinx2020_1_ug900-vivado-logic-simulation.pdf]

P34，Generating a Netslit

P162, Running Simulation Modes

//------------------------------------------------------------

查看工具

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70][]

[http://www.concept.de/GateVision.html][http_www.concept.de_GateVision.html]

[https_zhuanlan.zhihu.com_p_137433454]: https://zhuanlan.zhihu.com/p/137433454
[https_forums.xilinx.com_t5_Vivado_vivado_E7_94_9F_E6_88_90_E7_BD_91_E8_A1_A8-edf-_E6_96_87_E4_BB_B6-_E6_96_B0_E5_B7_A5_E7_A8_8B_E4_B8_AD_E4_B8_8D_E8_83_BD_E8_BF_9B_E8_A1_8C_E4_BB_BF_E7_9C_9F_m-p_1134183]: https://forums.xilinx.com/t5/Vivado/vivado%E7%94%9F%E6%88%90%E7%BD%91%E8%A1%A8-edf-%E6%96%87%E4%BB%B6-%E6%96%B0%E5%B7%A5%E7%A8%8B%E4%B8%AD%E4%B8%8D%E8%83%BD%E8%BF%9B%E8%A1%8C%E4%BB%BF%E7%9C%9F/m-p/1134183
[https_www.xilinx.com_support_documentation_sw_manuals_xilinx2020_1_ug900-vivado-logic-simulation.pdf]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug900-vivado-logic-simulation.pdf
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70]: /images/20230208/64b80fa90f474d26b32b81a04897b9a7.png
[http_www.concept.de_GateVision.html]: http://www.concept.de/GateVision.html