FPGA仿真及时序约束分析

快来打我* 2023-06-13 11:29 1阅读 0赞

建立保持时间：

![20191117152249400.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70][]

亚稳态：metastability

![20191117152835463.png][]

Slack:

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 1][]

Setup Slack

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 2][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 3][]

Hold slack:

![20191117233204342.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 4][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 5][]

Data Arrival Time

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 6][]

系统同步系统（当时钟和数据一起传时称为源同步系统，比如常见的SPI/I2C都有一个CLK信号）：

![20191117152138851.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 7][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 8][]

SDC命令简介：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 9][]

create\_clock

\-------------------------------------------------------------------------------------------------

set\_clock\_groups  -logically\_exclusive -physically\_exclusive -asynchronous -group  \[get\_clocks clkname -include\_generated\_clocks\]

1、逻辑互斥：对于设计中使用MUX时使用

2、物理互斥:  对于设计中没有路径交互、完全独立时使用

3、异步：对于设计中没有相位关系时使用，比如跨时钟域的路径就指定为异步

set\_clock\_groups 只能指定三个选项中的一个

\-------------------------------------------------------------------------------------------------

set\_clock\_uncertainty

\-------------------------------------------------------------------------------------------------

set\_max\_delay

\-------------------------------------------------------------------------------------------------

set\_input\_delay -max

set\_input\_delay -min

\-------------------------------------------------------------------------------------------------

set\_output\_delay -max

set\_output\_delay -min

\-------------------------------------------------------------------------------------------------

set\_false\_path

set\_muticycle\_path

--------------------

操作示例

在Quartus工具栏点击小时钟：

1、建立时序分析网表【第一次选择post-map\[初次创建SDC文件\],第二次选择post-fit】

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 10][]

![20191117231733372.png][]

2、

整理自：

1、<<FPGA深度分析>>

2、<<[逻辑电路设计 DE2-115 实战宝典][DE2-115]>>

3、综合与时序分析的设计约束 韩德强等 译

参考：

[http://xilinx.eetop.cn/viewnews-2637?tc=eml][http_xilinx.eetop.cn_viewnews-2637_tc_eml]

[http://xilinx.eetrend.com/blog/2019/100018570.html][http_xilinx.eetrend.com_blog_2019_100018570.html]

[20191117152249400.png]: https://img-blog.csdnimg.cn/20191117152249400.png
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[20191117152835463.png]: https://img-blog.csdnimg.cn/20191117152835463.png
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[20191117233204342.png]: https://img-blog.csdnimg.cn/20191117233204342.png
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[20191117231733372.png]: https://img-blog.csdnimg.cn/20191117231733372.png
[DE2-115]: http://www.terasic.com.cn/cgi-bin/page/archive.pl?Language=China&CategoryNo=&No=728
[http_xilinx.eetop.cn_viewnews-2637_tc_eml]: http://xilinx.eetop.cn/viewnews-2637?tc=eml
[http_xilinx.eetrend.com_blog_2019_100018570.html]: http://xilinx.eetrend.com/blog/2019/100018570.html